USB Device Controller
1586
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Universal Serial Bus (USB)
29.3.1.19 Transmit DMA Control Register n (TXDMAn)
This read/write register controls the operation of the transmit DMA channel n (n = 0, 1, 2).
Figure 29-46. Transmit DMA Control Register n (TXDMAn)
[address = FCF78A28h to FCF78A2Ch]
15
14
13
10
9
8
TXn_EOT
TXn_START
Reserved
TXn_TSC
R/W-0
R/W-0
R-0
R/W-0
7
0
TXn_TSC
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value at reset
Table 29-50. Transmit DMA Control Register n (TXDMAn) Field Descriptions
Bit
Field
Value
Description
15
TXn_EOT
Transmit DMA channel n end of transfer: the TXn_EOT bit can be either 0 or 1 for BULK DMA
transfer. When the USB device controller sets it to 1, this bit signals the core that the transfer size
set in TXDMAn.TXn_TSC is in bytes. A TX one interrupt (IRQ_SRC.TXn_DONE) is asserted with
the last IN transaction. If the number of bytes set in TXDMAn.TXn_TSC is a multiple of the endpoint
buffer size, the TX done interrupt is asserted only after an IN transaction with an empty data
packet. When cleared, the transfer size set in TXn_TSC is in full buffer size for the endpoint
selected (BULK only). A TX done interrupt is asserted when the last buffer is sent with the last IN
transaction. This mode is to be used for a partial bulk transfer of a large file exceeding 1023 bytes.
0
DMA transfer size is in buffers.
1
DMA transfer size is in bytes.
Value after system reset or USB reset is low.
14
TXn_START
Transmit DMA channel n start. The USB device controller sets this bit to tell the device that the
main DMA system is ready to transmit the number of bytes or buffers. Once set, the DMA transfer
cannot be interrupted, unless the USB device controller clears the endpoint in the TXDMA_CFG
register. A write 0 into this bit has no effect and a read to this bit always returns 0. The
IRQ_SRC.TXn_DONE interrupt bit is asserted when the DMA transfer ends.
0
No action.
1
DMA transfer start.
Always reads 0.
13-10
Reserved
0
Reserved
9-0
TXn_TSC
0-3FFh
Transmit DMA channel n transfer size counter. The binary encoded value from 0 to 1023, which the
USB device controller writes into this register, corresponds to the number of bytes or number of
buffer transfers (function of TXDMAn.TXn_EOT) to be transmitted by the transmit DMA channel n.
When read, the register reflects the number of bytes/buffers the USB device has still to transmit.
Read mode is only provided for software debug purposes.
Note: For ISO transfer, the user must verify that the set value does not exceed the ISO FIFO size
for the endpoint. There is no hardware mechanism to prevent this situation. If this situation occurs,
results are unpredictable.
Note: For bulk transfer, when TXDMAn.TXn_EOT = 0, a set value of TXDMAn.TXn_TSC = 0
means 1024 buffers and not 0. The counter then operates in the following way: 000, 3FF, 3FE,
0001, 000, stop. When TXDMAn.TXn_EOT = 1, a set value of TXDMAn.TXn_TSC = 0 a NULL
packet is sent in response to the next IN token.
Values after system reset or USB reset are low (all 10 bits).
