DMA_REQ[31:0]
CH15ASI[5:0]
CH14ASI[5:0]
CH1ASI[5:0]
CH1ASI[5:0]
Ch chain0
Ch Sel0
Ch chain1
Ch Sel1
Ch chain14
Ch Sel14
Ch chain15
Ch Sel15
0
0
0
0
Pending
Register
Bit 0
Bit 2
Bit 14
Bit 15
Bit 1
Module Operation
559
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Direct Memory Access Controller (DMA) Module
Figure 16-16. Example of Channel Chaining
16.2.14 Memory Protection
The DMA controller is capable of access to the full address range of the device. The protection
mechanism allows the protection of up to four memory regions to restrict accesses to those address
ranges. This will allow the application to protect critical application data from unintentionally being
accessed by the DMA controller.
16.2.14.1 Protection Mechanism
The memory protection mechanism consists of the access privilege for a given memory region, the start
and end address for the region, and notification of an access violation for the protected region.
Each region to be protected is configured by software by writing the start address and end address for
each region into the DMA Memory Protection Registers, DMAMPRxS and DMAMPRxE. The definition of
these registers can be found starting at
. Any region in the valid address space can be
protected from inappropriate accesses.
The access privileges can be set to one of four permission settings:
•
Full access
•
Read only access
•
Write only access
•
No access
The permissions for a given region are selected by writing the appropriate values in the DMA Memory
Protection Control Register (
).
NOTE:
If the regions defined by the start and end addresses overlap, the region defined first in the
register space determines the access privilege. For example, if region 0 and region 1
overlap, the access permissions defined for region 0 will take precedence since region 0
registers are before region 1.
