Clocks
122
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Architecture
2.4.6.4.1 DCC1
Table 2-14. DCC1 Counter 0 Clock Inputs
Clock Source [3-0]
Clock / Signal Name
All other values
Oscillator (OSCIN)
0x5
HF LPO
0xA
Test clock (TCK)
Table 2-15. DCC1 Counter 1 Clock / Signal Inputs
Key [3-0]
Clock Source [3-0]
Clock / Signal Name
0xA
0x0
PLL1 free-running clock output
0x1
PLL2 free-running clock output
0x2
LF LPO
0x3
HF LPO
0x4
Reserved
0x5
EXTCLKIN1
0x6
EXTCLKIN2
0x7
Reserved
0x8-0xF
VCLK
All other values
Any value
N2HET1[31]
As can be seen, the main oscillator (OSCIN) can be used for counter 0 as a “known-good” reference
clock. The clock for counter 1 can be selected from among 8 options. See
for more details on
the DCC usage.
2.4.6.4.2 DCC2
Table 2-16. DCC2 Counter 0 Clock Inputs
Clock Source [3-0]
Clock / Signal Name
All other values
Oscillator (OSCIN)
0xA
Test clock (TCK)
Table 2-17. DCC2 Counter 1 Clock / Signal Inputs
Key [3-0]
Clock Source [3-0]
Clock / Signal Name
0xA
0x0-0x7
Reserved
0x8-0xF
VCLK
All other values
Any value
N2HET2[0]
As can be seen, the main oscillator (OSCIN) can be used for counter 0 as a “known-good” reference
clock. The clock for counter 1 can be selected from among 2 options. See
for more details on
the DCC usage.
