Module Operation
977
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
High-End Timer Transfer Unit (HTU) Module
21.2.5 Memory Protection
This feature allows restricting accesses to certain areas in memory in order to protect critical application
data from unintentionally being manipulated by the HTU.
If the HTU memory protection feature is disabled, the full 4 GB address range can be accessed by the
HTU without exception. There are two memory regions that start and end addresses can be configured.
With the HTU memory protection feature enabled, read and write accesses by the HTU IFADDRA and
IFADDRB registers inside the defined regions are allowed. HTU access to its tightly-coupled memory is
independent of the MPU, it routes through the dedicated HTU/N2HET bus using the IHADDR bits in the
IHADDRCT register. See
for details on the tightly-coupled bus. For accesses outside the
regions, one of two modes is configurable:
•
Any access performed by the HTU is forbidden and will be signaled to the ESM module. Write
accesses will be blocked.
•
Read access is allowed but write access will be blocked and signaled to the ESM module.
To use one region only, REG01ENA must be 0. Bits ACCR01, INTENA01, and register settings of MP1S
and MP1E will be ignored.
To use both regions, the following rules must be followed:
1. Memory mapped region 0 covers a lower memory area as Memory mapped region 1.
2. REG01ENA is a 1 and REG0ENA is a 0.
3. ACCR01 is set for the desired access type, ACCR0 is ignored.
4. INTENA01 is set for the desired action, INTENA0 is ignored.
If an element transfer of DCP x generates a memory protection error, then:
1. The element counter of DCP x is cleared.
2. All new element transfers on DCP x are stopped.
3. The active busy bit of DCP x is cleared.
4. DCP x is disabled in the CPENA register. The DCPs other than DCP x will not be affected.
5. The FT flag will be set.
6. An error is signaled to the ESM module.
21.2.6 Control Packet RAM Parity Checking
The HTU module can detect parity errors in the DCP (Double Control Packet) RAM. DCP RAM parity
checking is implemented using one parity bit per byte. Even or odd parity checking can be selected in the
DEVCR1 register of the system module and can be enabled/disabled by a 4-bit key in the PCR register.
During a read access to the DCP RAM, the parity is calculated based on the data read from the RAM and
compared with the good parity value stored in the parity bits. The parity check is performed when the HTU
or any other master (for example, CPU) makes a read access to the DCP RAM. A read access within the
RAM section of an initial or current DCP checks all 16 bytes of the DCP at a time (see also DCP memory
map). For example, if a byte read access happens for DCP RAM address 0, but there is a parity error at
byte address Ch then the parity error will occur and the captured parity address will be Ch and not 0. The
address of the byte in which the error occurred can be read from the PAR register. If successive DCP
RAM read accesses generate multiple parity errors, only the address of the first detected error will be
captured and the PAR register will not be updated by subsequent errors until it is read by the application.
When multiple errors in a 16 byte word are detected, only the address of the lowest byte will be captured.
The application can decide whether to stop any transfers when a parity error is detected or to continue
transferring data. If the COPE (Continue On Parity Error) bit is 0 and parity checking is enabled, then the
HTU will not start the frame and the corresponding DCP will be automatically disabled in the CPENA
register. If a master other than the HTU (for example, CPU) reads the RAM section of DCP x and a parity
error is detected during this read access, while the parity check is enabled and the COPE bit is 0, then the
DCP x will be automatically disabled in the CPENA register. If a frame for this DCP x is ongoing during
