failure
ERROR
t
ERROR_low
ERROR pin reset request
failure
ERROR
t
ERROR_low
ERROR pin reset request
failure
ERROR
t
ERROR_low
)
1
(
_
+
´
=
LTCP
t
t
VCLK
low
ERROR
Module Operation
412
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Error Signaling Module (ESM)
12.2.2 ERROR Pin Timing
The ERROR pin is an active-low function. The state of the pin is also readable from ERROR Pin Status
Register (ESMEPSR). The pin is in a high-impedance state during power-on reset. Once the ESM module
drives the ERROR pin low, it remains in this state for the time specified by the Low-Time Counter Preload
register (LTCPR). Based on the time period of the peripheral clock (VCLK), the total active time of the
ERROR pin can be calculated as:
(22)
Once this period expires, the ERROR pin is set to high in case the reset of the ERROR pin was
requested. This request is done by writing an appropriate key (5h) to the key register (ESMEKR) during
the ERROR pin low time. Here are a few examples:
Example 1: ESM detects a failure and drives the ERROR pin low. No ERROR pin reset is requested. The
ERROR pin continues outputting low until power on reset occurs.
Figure 12-4. ERROR Pin Timing - Example 1
Example 2: ESM detects a failure and drives the ERROR pin low. An ERROR pin reset request is
received before t
ERROR_low
expires. In this case, the ERROR pin is set to high immediately after t
ERROR_low
expires.
Figure 12-5. ERROR Pin Timing - Example 2
Example 3: ESM detects a failure and drives the ERROR pin low. An ERROR pin reset request is
received after t
ERROR_low
expires. In this case, the ERROR pin is set to high immediately after ERROR pin
reset request is received.
Figure 12-6. ERROR Pin Timing - Example 3
