SCI Configurations
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SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Serial Communication Interface (SCI) Module
26.5 SCI Configurations
Before the SCI sends or receives data, its registers should be properly configured. Upon power-up or a
system-level reset, each bit in the SCI registers is set to a default state. The registers are writable only
after the RESET bit in the SCIGCR0 register is set to 1. Of particular importance is the SWnRST bit in the
SCIGCR1 register. The SWnRST is an active-low bit initialized to 0 and keeps the SCI in a reset state
until it is programmed to 1. Therefore, all SCI configuration should be completed before a 1 is written to
the SWnRST bit.
The following list details the configuration steps that software should perform prior to the transmission or
reception of data. As long as the SWnRST bit is cleared to 0 the entire time that the SCI is being
configured, the order in which the registers are programmed is not important.
•
Enable SCI by setting the RESET bit to 1.
•
Clear the SWnRST bit to 0 before SCI is configured.
•
Select the desired frame format by programming the SCIGCR1 register.
•
Set both the RX FUNC and TX FUNC bits in SCIPIO0 to 1 to configure the SCIRX and SCITX pins for
SCI functionality.
•
Select the baud rate to be used for communication by programming the BRS register.
•
Set the CLOCK bit in SCIGCR1 to 1 to select the internal clock.
•
Set the CONT bit in SCIGCR1 to 1 to make SCI not halt for an emulation breakpoint until its current
reception or transmission is complete (this bit is used only in an emulation environment).
•
Set LOOP BACK bit in SCIGCR1 to 1 to connect the transmitter to the receiver internally (this feature
is used to perform a self-test).
•
Set the RXENA bit in SCIGCR1 to 1, if data is to be received.
•
Set the TXENA bitin SCIGCR1 to 1, if data is to be transmitted.
•
Set the SWnRST bit to 1 after SCI is configured.
•
Perform receiving or transmitting data (see
and
).
26.5.1 Receiving Data
The SCI receiver is enabled to receive messages if both the RX FUNC bit and the RXENA bit are set to 1.
If the RX FUNC bit is not set, the SCIRX pin functions as a general-purpose I/O pin rather than as an SCI
function pin. After a valid idle period is detected, data is automatically received as it arrives on the SCIRX
pin.
SCI sets the RXRDY bit when it transfers newly received data from SCIRXSHF to SCIRD. The SCI clears
the RXRDY bit after the new data in SCIRD has been read. Also, as data is transferred from SCIRXSHF
to SCIRD, the SCI sets the FE, OE, or PE flags if any of these error conditions were detected in the
received data. These error conditions are supported with configurable interrupt capability. The wake-up
and break-detect status bits are also set if one of these errors occurs, but they do not necessarily occur at
the same time that new data is being loaded into SCIRD.
You can receive data by:
1. Polling Receive Ready Flag
2. Receive Interrupt
3. DMA
In polling method, software can poll for the RXRDY bit and read the data from SCIRD register once
RXRDY is set high. The CPU is unnecessarily overloaded by selecting the polling method. To avoid this,
you can use either the interrupt or DMA method. To use the interrupt method, the SET RX INT bit is set.
To use the DMA method, the SET RX DMA bit is set. Either an interrupt or a DMA request is generated
the moment the RXRDY bit is set.
