Control Registers
1203
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
24.9.37 DMA Large Count (DMACNTLEN)
Figure 24-67. DMA Large Count Register (DMACNTLEN) [offset = 118h]
31
16
Reserved
R-0
15
1
0
Reserved
LARGE_COUNT
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -
n
= value after reset
Table 24-45. MibSPI DMA Large Count Register (DMACNTLEN) Field Descriptions
Bit
Field
Value
Description
31-1
Reserved
0
Reads return 0. Writes have no effect.
0
LARGE_COUNT
Select either the 16-bit DMAxCOUNT counters or the smaller counters in DMAxCTRL.
0
Select the DMAxCTRL counters. Writes to the DMAxCTRL register will modify the ICOUNT
value. Reading ICOUNT and COUNT can be done from the DMAxCTRL register. The
DMAxCOUNT register should not be used since any write to this register will be overwritten by
a subsequent write to the DMAxCTRL register to set the TXDMAENA or RXDMAENA bits.
1
Select the DMAxCOUNT counters. Writes to the DMAxCTRL register will not modify the
ICOUNT value. The ICOUNT value must be written to in the DMAxCOUNT register before the
RXDMAENA or TXDMAENA bits are set in the DMAxCTRL register. The DMAxCOUNT register
should be used for reading COUNT or ICOUNT.
24.9.38 Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL)
Figure 24-68. Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL)
[offset = 120h]
31
16
Reserved
R-0
15
9
8
7
4
3
0
Reserved
PTESTEN
Reserved
EDEN
R-0
R/WP-0
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -
n
= value after reset
Table 24-46. Multi-buffer RAM Uncorrectable Parity Error Control Register (UERRCTRL)
Field Descriptions
Bit
Field
Value
Description
31-9
Reserved
0
Reads return 0. Writes have no effect.
8
PTESTEN
Parity memory test enable. This bit maps the parity bits corresponding to multi-buffer RAM
locations into the peripheral RAM frame to make them accessible by the CPU. See
for further details about parity memory testing.
0
Parity bits are not memory-mapped.
1
Parity bits are memory-mapped.
7-4
Reserved
0
Reads return 0. Writes have no effect.
3-0
EDEN
Error detection enable. These bits enable parity error detection.
5h
Parity error detection logic (default) is disabled.
All Other Values
Parity error detection logic is enabled.
Note: It is recommended to write a 1010 to enable error detection, to guard against a
soft error from disabling parity error detect
