Control Registers
1678
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Data Modification Module (DMM)
30.3.4 DMM Interrupt Level Register (DMMINTLVL)
This register contains the interrupt level bits for error interrupts and normal interrupts.
Figure 30-10. DMM Interrupt Level Register (DMMINTLVL) [offset = 0Ch]
31
24
Reserved
R-0
23
18
17
16
Reserved
PROG_BUFF
EO_BUFF
R-0
R/WP-0
R/WP-0
15
14
13
12
11
10
9
8
DEST3REG2
DEST3REG1
DEST2REG2
DEST2REG1
DEST1REG2
DEST1REG1
DEST0REG2
DEST0REG1
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
7
6
5
4
3
2
1
0
BUSERROR
BUFF_OVF
SRC_OVF
DEST3_ERR
DEST2_ERR
DEST1_ERR
DEST0_ERR
PACKET_
ERR_INT
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -
n
= value after reset
Table 30-10. DMM Interrupt Level Register (DMMINTLVL) Field Descriptions
Bit
Field
Value
Description
31-18
Reserved
0
Reads returns 0. Writes have no effect.
17
PROG_BUFF
Programmable Buffer Interrupt Level
User and privilege mode read, privilege mode write:
0
Interrupt mapped to level 0.
1
Interrupt mapped to level 1.
16
EO_BUFF
End of Buffer Interrupt Level
User and privilege mode read, privilege mode write:
0
Interrupt mapped to level 0.
1
Interrupt mapped to level 1.
15
DEST3REG2
Destination 3 Region 2 Interrupt Level
User and privilege mode read, privilege mode write:
0
Interrupt mapped to level 0.
1
Interrupt mapped to level 1.
14
DEST3REG1
Destination 3 Region 1 Interrupt Level
User and privilege mode read, privilege mode write:
0
Interrupt mapped to level 0.
1
Interrupt mapped to level 1.
13
DEST2REG2
Destination 2 Region 2 Interrupt Level
User and privilege mode read, privilege mode write:
0
Interrupt mapped to level 0.
1
Interrupt mapped to level 1.
12
DEST2REG1
Destination 2 Region 1 Interrupt Level
User and privilege mode read, privilege mode write:
0
Interrupt mapped to level 0.
1
Interrupt mapped to level 1.
11
DEST1REG2
Destination 1 Region 2 Interrupt Level
User and privilege mode read, privilege mode write:
0
Interrupt mapped to level 0.
1
Interrupt mapped to level 1.