Texas Instruments RM48 series, Technical Reference Manual

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System and Peripheral Control Registers
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138 SPNU503C – March 2018
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Architecture
2.5.1.16 GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC)
The GHVSRC register, shown in Figure 2-21 and described in Table 2-35 , controls the clock source
configuration for the GCLK, HCLK, VCLK and VCLK2 clock domains.
Figure 2-21. GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC) [offset = 48h]
31 28 27 24 23 20 19 16
Reserved GHVWAKE Reserved HVLPM
R-0 R/WP-0 R-0 R/WP-0
15 4 3 0
Reserved GHVSRC
R-0 R/WP-0
LEGEND: R = Read only; R/W = Read/Write; WP = Write in privileged mode only; - n = value after reset
Table 2-35. GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC) Field Descriptions
Bit Field Value Description
31-28 Reserved 0 Reads return 0. Writes have no effect.
27-24 GHVWAKE GCLK, HCLK, VCLK, VCLK2 source on wakeup.
0 Clock source0 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
1h Clock source1 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
2h Clock source2 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
3h Clock source3 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
4h Clock source4 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
5h Clock source5 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
6h Clock source6 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
7h Clock source7 is the source for GCLK, HCLK, VCLK, VCLK2 on wakeup.
8h-Fh Reserved
23-20 Reserved 0 Reads return 0. Writes have no effect.
19-16 HVLPM HCLK, VCLK, VCLK2 source on wakeup when GCLK is turned off.
0 Clock source0 is the source for HCLK, VCLK, VCLK2 on wakeup.
1h Clock source1 is the source for HCLK, VCLK, VCLK2 on wakeup.
2h Clock source2 is the source for HCLK, VCLK, VCLK2 on wakeup.
3h Clock source3 is the source for HCLK, VCLK, VCLK2 on wakeup.
4h Clock source4 is the source for HCLK, VCLK, VCLK2 on wakeup.
5h Clock source5 is the source for HCLK, VCLK, VCLK2 on wakeup.
6h Clock source6 is the source for HCLK, VCLK, VCLK2 on wakeup.
7h Clock source7 is the source for HCLK, VCLK, VCLK2 on wakeup.
8h-Fh Reserved
15-4 Reserved 0 Reads return 0. Writes have no effect.
3-0 GHVSRC GCLK, HCLK, VCLK, VCLK2 current source.
Note: The GHVSRC[3-0] bits are updated with the HVLPM[3-0] setting when GCLK is turned
off, and are updated with the GHVWAKE[3-0] setting on system wakeup.
0 Clock source0 is the source for GCLK, HCLK, VCLK, VCLK2.
1h Clock source1 is the source for GCLK, HCLK, VCLK, VCLK2.
2h Clock source2 is the source for GCLK, HCLK, VCLK, VCLK2.
3h Clock source3 is the source for GCLK, HCLK, VCLK, VCLK2.
4h Clock source4 is the source for GCLK, HCLK, VCLK, VCLK2.
5h Clock source5 is the source for GCLK, HCLK, VCLK, VCLK2.
6h Clock source6 is the source for GCLK, HCLK, VCLK, VCLK2.
7h Clock source7 is the source for GCLK, HCLK, VCLK, VCLK2.
8h-Fh Reserved