Texas Instruments RM48 series, Technical Reference Manual

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)) 2 ( ) 2 )(( 1 2 (
2
d CCKH I d CCKL I CPSC I
kFrequency CInputCloc I
kFrequency MasterCloc
+ + + +
=
) 2 ( ) 2 (
d CCKH I d CCKL I
kFrequency ModuleCloc
kFrequency MasterCloc
+ + +
=
) 1 2 (
2
+
=
CPSC I
kFrequency CInputCloc I
kFrequency ModuleCloc
Generator
Clock
OSCIN
I2C Module
(VBUS_CLK)
I2C Input Clock
I2CPSC
I2CCKL
I2CCKH
Module Clock for
I2C Module Operation
on SCL pin
Master Clock
To I2C Bus
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Overview
1375 SPNU503C – March 2018
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Inter-Integrated Circuit (I2C) Module
27.1.3 Clock Generation
As shown in Figure 27-3 , the I2C module uses the input clock generated from the device clock generator
to generate the module clock and master clock. The I2C input clock is the device peripheral clock
(VBUS_CLK). The clock is then divided twice more inside the I2C module to produce the module clock
and the master clock.
Figure 27-3. Clocking Diagram for the I2C Module
The module clock determines the frequency at which the I2C module operates. A programmable prescaler
in the I2C module divides down the input clock to produce the module clock. To specify the divide-down
value, initialize the I2CPSC field of the prescaler register, I2CPSC. The resulting frequency is:
(59)
The module clock frequency must be between 6.7MHz and 13.3MHz. The prescaler can only be initialized
while the I2C module is in the reset state (IRS = 0 in I2CMDR). The prescaled frequency takes effect only
when IRS is changed to 1. Changing the I2CPSC value while IRS = 1 has no effect.
The master clock appears on the SCL pin when the I2C module is configured to be a master on the I2C
bus. This clock controls the timing of the communication between the I2C module and a slave. As shown
in
Figure 27-3 , a second clock divider in the I2C module divides down the module clock to produce the
master clock. The clock divider uses the I2CCKL to divide down the low portion of the module clock signal
and uses the I2CCKH to divide down the high portion of the module clock signal.
The resulting frequency is:
(60)
(61)
where d depends on the value of I2CPSC:
I2CPSC d
0 7
1 6
Greater than 1 5