USB Device Controller
1642
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Universal Serial Bus (USB)
29.3.27 DMA Operation
The USB device controller provides support for six DMA channels. Three receive DMA channels are
reserved to OUT transfers (ISO or non-ISO) and three transmit DMA channels are reserved to IN transfers
(ISO or non-ISO). It is not possible to operate DMA transactions on control EP0.
NOTE:
The CPU must not access an endpoint used in a DMA transfer through the EP_NUM, CTRL,
and STAT_FLG registers (in DMA, this remark applies after the CPU has set the
CTRL.SET_FIFO_EN bit to enable the RX DMA transfer). In particular, the CPU must not set
the halt feature while the endpoint is selected in the RXDMA_CFG register.
To use the DMA channels properly, you must set the DMA configuration during the address
state interrupt (DS_CHANGE).
The parameters used for DMA transactions (FIFO size, ISO endpoint, double-buffering, and pointers) are
those defined for the associated endpoint.
29.3.27.1 Receive DMA Channels Overview
Receive DMA channels are programmed via the three RXDMA control registers. Each channel is assigned
to a given endpoint number by assigning a non-zero value in RXDMA_CFG.RXDMAn_EP fields (a 0 value
means the DMA channel is deselected). Received OUT data must be read when an RX DMA request is
active, through the register DATA_DMA. The RX FIFO accessed is that of the endpoint for which the DMA
request is active (only one RX DMA request is active at a time).
The USB device controller receive DMA channels 0, 1, and 2 are connected to the device System DMA
controller requests # 15, 19, and 29, respectively.
29.3.27.2
Non-Isochronous OUT (USB HOST -> CPU) DMA Transactions
During non-ISO transfers to a DMA operated OUT endpoint, a request to the CPU DMA controller is
generated when data have been placed into endpoint FIFO and must be read. ACK and NAK interrupts
are always disabled automatically by the core for DMA operated endpoints.
There are two dedicated maskable interrupts per DMA channel to control non-ISO OUT transfers.
29.3.27.3 End of Transfer Interrupt (IRQ_SRC.RXn_EOT)
This interrupt signals that the core has detected an end-of-transfer (EOT). EOT occurs in the two following
cases:
•
When the last valid transaction to the endpoint is either an empty packet (ACK and buffer empty) or a
packet whose size is less than the physical endpoint buffer size (ACK and buffer not full)
•
When the number of received transactions has reached the programmed value in the
RXDMAn.RXn_TC field, if the RXDMAn.RXn_STOP bit has been set by the CPU
After an end of transfer interrupt, the CPU must set CTRL.SET_FIFO_EN for the endpoint to reenable the
channel.
The CPU must not initiate a new RX DMA transfer until it receives an end-of-transfer interrupt.
29.3.27.4 Transaction Count Interrupt (IRQ_SRC.RXn_CNT)
The intent of this interrupt is watermark control. It can be used by the CPU to monitor the file size of
incoming transfers and take appropriate actions if, for instance, the file being received exceeds an
expected size.
A transaction count interrupt does not disable the ongoing DMA transfer.
A transaction count interrupt occurs each time the number of received transactions (and not bytes) has
reached the programmed value in the receive transaction counter for the DMA channel. One transaction
has a size equal to the buffer size of the selected non-ISO endpoint. RXn_COUNT interrupt is asserted
even if RXDMAn.RXn_STOP has been set; in that case, both RXn_COUNT and RXn_EOT interrupts are
asserted (see
through
).
