Memory Organization
106
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Architecture
When the CPU detects an ECC single-, or double-bit error on a read from the flash memory, it signals this
on a dedicated “
Event
” bus. This event bus signaling is also not enabled by default and must be enabled
by the application. The following code example can be used to enable the CPU event signaling.
MRC p15,#0,r1,c9,c12,#0
;Enabling Event monitor states
ORR r1, r1, #0x00000010
MCR p15,#0,r1,c9,c12,#0
;Set 4th bit ('X') of PMNC register
MRC p15,#0,r1,c9,c12,#0
The digital logic that interfaces the ARM Cortex-R4F CPU to the flash banks captures the ECC error
events signaled by the CPU, and in turn generates error signals that are input to the central Error
Signaling Module (ESM).
2.2.4 On-Chip SRAM
Several SRAM modules are implemented on the device to support the functionality of the modules
included.
Reads from the CPU data RAM are protected by ECC calculated inside the CPU. Reads from all other
memories are protected by configurable odd or even parity that is evaluated in parallel with the actual
read.
The RM48x microcontrollers are targeted towards safety-critical applications, and it is critical for any
failures in the on-chip SRAM modules to be identified before these modules are used for safety-critical
functions. These microcontrollers support a Programmable Built-In Self-Test (PBIST) mechanism that is
used to test each on-chip SRAM module for faults. The PBIST is usually run on device start-up as it is a
destructive test and all contents of the tested SRAM module are overwritten during the test.
The microcontrollers also support a hardware-based auto-initialization of on-chip SRAM modules. This
process also takes into account the read protection scheme implemented for each SRAM module – ECC
or parity.
TI recommends that the PBIST routines be executed on the SRAM modules prior to the auto-initialization.
The following section describe these two processes.
2.2.4.1
PBIST RAM Grouping and Algorithm Mapping For On-Chip SRAM Modules
shows the groupings of the various on-chip memories for PBIST. It also lists the memory types
and their assigned RAM Group Select (RGS) and Return Data Select (RDS). See
for more
details on the usage of the RGS and RDS information.
Table 2-5. PBIST Memory Grouping
Memory
RAM Group #
Memory Type
RGS
RDS
PBIST_ROM
1
ROM
1
0
STC_ROM
2
ROM
2
0
DCAN1
3
Dual-port
3
0 .. 5
DCAN2
4
Dual-port
4
0 .. 5
DCAN3
5
Dual-port
5
0 .. 5
ESRAM1
6
Single-port
6
0/1 .. 4
MIBSPI1
7
Dual-port
7
0 .. 3
MIBSPI3
8
Dual-port
7
4 .. 7
MIBSPI5
9
Dual-port
7
8 .. 11
VIM
10
Dual-port
8
0 .. 1
MIBADC1
11
Dual-port
9
0
DMA
12
Dual-port
10
0 .. 5
N2HET1
13
Dual-port
11
0 .. 11
HET TU1
14
Dual-port
12
0 .. 5
RTP
15
Dual-port
13
0 .. 8
MIBADC2
18
Dual-port
15
0
