Application Self-Test Flow
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SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
CPU Self-Test Controller (STC) Module
8.2
Application Self-Test Flow
This section describes the STC module configuration and the application self-test flow that the user should
follow for successful execution. The following two configurations must be part of the STC initialization
code:
•
STC clock rate configuration, STC clock divider (STCCLKDIV) register in system module is used to
divide HCLK (system clock) to generate STCCLK
•
Clear SYSESR register before triggering an STC test
8.2.1 STC Module Configuration
•
Configure the test interval count using STCGCR0[31:16] register. A maximum of 24 intervals are
supported in the device. You can run 24 intervals together or in slices. If the tests are run in slices, the
user software can specify to the self-test controller whether to continue the run from the next interval
onwards or to restart from interval 0 using bit STCGCR0[0]. This bit gets reset after the completion of
the self-test run.
•
Configure self-test run timeout counter preload register STCTPR. This register contains the total
number of VBUS clock cycles it will take before a self-test timeout error (TO_ERR) will be triggered
after the initiation of the self-test run.
•
Enable CPU self-test by writing the enable key to STCGCR1 register.
8.2.2 Context Saving
STC generates a CPU reset after completion of the test regardless of pass or fail. You can run the STC
test during startup or can divide STC into 24 or fewer intervals and run them during normal operation.
If STC is ran only on startup, the user software need not save the CPU contents since the reset caused
will go through all startup configurations. You should check the STCGSTAT register for the self-test status
before going to the application software.
If STC is divided into intervals and ran, user software must save the CPU contents and reload them after
the CPU reset caused by the completion of the STC test interval. The check for STC status should bypass
STC run if the reset is caused by an STC run to prevent a cyclic reset, that is, if reset is caused by STC
the second time through, then it should not be ran again. You should also check the STCGSTAT register
for the self-test status before restoring the application software.
Following are some of the registers that are required to be backed up before and restored after self-test:
1. CPU core registers (all modes R0-R15, PC, CPSR)
2. CP15 System Control Coprocessor registers - MPU control and configuration registers, Auxiliary
Control Register used to Enable ECC, Fault Status Register etc.
3. CP13 Coprocessor Registers - FPU configuration registers, General Purpose Registers
4. Hardware Break Point and watch point registers like BVR, BSR, WVR, WSR etc.
For more information on the CPU reset, refer to the
-R4F Technical Reference Manual
.
NOTE:
Check all reset source flags in the SYSESR register after a CPU BIST execution. If a flag, in
addition to CPU reset, is set, clear the CPU reset flag and service the other reset sources
accordingly.
8.2.3 Entering CPU Idle Mode
After enabling the STC test by writing the STC enable key, the test is triggered only after the CPU is taken
to idle mode by executing the CPU Idle Instruction
asm(“ WFI”).
