General Description
343
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
CPU Self-Test Controller (STC) Module
8.1
General Description
The CPU self-test controller (STC) is used to test the ARM-CPU core using the Deterministic Logic Built-in
Self-Test (LBIST) Controller as the test engine. To achieve better coverage for the self-test of complex
cores like Cortex-R4, on-chip logic BIST is the preferred solution.
8.1.1 CPU Self-Test Controller Features
The CPU self-test controller has the following features:
•
Capable of running the complete test as well as running a few intervals at a time
–
Ability to continue from the last executed interval (test set) as well as the ability to restart from the
beginning (first test set)
–
Total of 24 intervals supported in this device
•
Complete isolation of the self-tested CPU core from the rest of the system during the self-test run
–
The self-tested CPU core master bus transaction signals are configured to be in idle mode during
the self-test run
–
Any master access to the CPU core under self-test (example: DMA access to CPU TCM) will be
held until the completion of the self-test
•
Ability to capture the failure interval number
•
Timeout counter for the CPU self-test run as a fail-safe feature
•
Able to read the MISR data (shifted from LBIST controller) of the last executed interval of the self-test
run for debugging purposes
•
STCCLK determines the self-test execution speed, STC clock divider (STCCLKDIV) register in the
system module is used to divide HCLK (system clock) to generate STCCLK
8.1.2 STC Block Diagram
STC module provides an interface to the LBIST controller implemented on the core.
The CPU STC is composed of following blocks of logic:
•
ROM Interface
•
FSM and Sequence Control
•
Register Block
•
Peripheral Bus Interface (VBUSP Interface)
•
STC Bypass/ATE Interface
8.1.2.1
ROM Interface
This block handles the ROM address and control signal generation to read the self-test microcode from
the ROM. The test microcode and golden signature value for each interval are stored in ROM.
8.1.2.1.1 FSM and Sequence Control
This block generates the signals and data to the LBIST controller based on the seed, test_type and scan
chain depth.
8.1.2.1.2 Clock Control
The CLOCK CNTRL sub-block handles the internal clock selection and clock generation for the ROM and
LBIST controller.
8.1.2.2
Register Block
This block handles the control of the self-test controller. This block contains various configuration and
status registers that provide the result of a self-test run. These registers are memory-mapped and
accessible through the Peripheral Bus (VBUSP) Interface. This block controls the reseeding (reloading the
existing seed of the PRPG) in the LBIST controller.
