Peripheral Bus
DMAREQ
IRQ
32
5
READ Bus
WRITE Bus
Register Bank
Local RAM (with parity)
FIFO B
Port B
Overview
542
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Direct Memory Access Controller (DMA) Module
16.1 Overview
The DMA controller is used to transfer data between two locations in the memory map in the background
of CPU operations. Typically, the DMA is used to:
•
Transfer blocks of data between external and internal data memories
•
Restructure portions of internal data memory
•
Continually service a peripheral
•
Page program sections to internal program memory
16.1.1 Main Features
•
CPU independent data transfer
•
One master port - PortB (64-bits wide) that interfaces microcontrollers Memory System.
•
FIFO buffer (4 entries deep and each 64-bits wide)
•
Channel control information is stored in RAM protected by parity
•
16 channels with individual enable
•
Channel chaining capability
•
32 peripheral DMA requests
•
Hardware and Software DMA requests
•
8-, 16-, 32-, or 64-bit transactions supported
•
Multiple addressing modes for source/destination (fixed, increment, offset)
•
Auto-initiation
•
Power-management mode
•
Memory Protection for the address range DMA can access with four configurable memory regions
16.1.1.1 Block Diagram
gives a detailed view of the DMA internal architecture. DMA data read and write access
happens through Port B. FIFO B is 4 levels deep and 64-bits wide. 32 DMA requests go into the DMA that
can trigger DMA transfers. Five interrupt request lines go out of the DMA to signal that a certain transfer
status is reached. Register banks hold the memory-mapped DMA configuration registers. Local RAM
consists of DMA control packets and is secured by parity. All the programming / configuration of the DMA
controller is done via the Peripheral bus.
Figure 16-1. DMA Block Diagram
