Instruction Set
906
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
High-End Timer (N2HET) Module
20.6.3.4 ADC, ADD, AND, OR, SBB, SUB, XOR
Syntax
ADC | ADD | AND | OR | SBB | SUB | XOR {
src1 = { ZERO | IMM | A | B | R | S | T | ONES | REM | REMP }
src2 = { ZERO | IMM | A | B | R | S | T | ONES }
dest = { NONE | IMM | A | B | R | S | T }
[rdest = { NONE | REM | REMP }]
[brk={OFF | ON}]
[next={label | 9-bit unsigned integer}]
[remote={label | 9-bit unsigned integer}]
[control={OFF | ON}]
[init={OFF | ON}]
[smode = {LSL | CSL | LSR | CSR | RR | CRR | ASR }]
[scount = {5 bit unsigned integer}]
[data={25-bit unsigned integer}]
[hr_data={7-bit unsigned integer}]
}
Figure 20-120. ADC, ADD, AND, OR, SBB, SUB, XOR Program Field (P31:P0)
31
26 25
23
22
21
13 12
9
8
0
0
Reserved
BRK
Next program address
0100
Remote address
6
3
1
9
4
9
Figure 20-121. ADC, ADD, AND, OR, SBB, SUB, XOR Control Field (C31:C0)
31
27
26
25
23
22
19
18
16
Reserved
Control
Sub Opcode
Src1
Src2
5
1
3
4
3
15
13
12
8
7
6
5
4
3
2
1
0
Smode
Scount
Ext. Reg
Init flag
1
Rdest
Register select
Res.
3
5
1
1
1
2
2
1
Figure 20-122. ADC, ADD, AND, OR, SBB, SUB, XOR Data Field (D31:D0)
31
7
6
0
Data
HR Data
25
7
Cycles
One to three cycles, depending on operands selected. (See
Register modified
Selected register (A, B, R, S, T, or NONE)
Description
This instruction performs the specified 32-bit arithmetic or logical operation on
operands src1 and src2, followed by an optional shift/rotate step. The result of
this operation is then stored to either an N2HET register or the immediate
data field of the instruction. In addition, the same result may be stored in a
remote data field or the least signficant bits of a remote instruction program
field (P[8:0]). Bits P[8:0] of the program field are used by most instructions
formats to hold the remote address that the instruction operates on, so the
ability to update this field programatically makes it easier to write subroutines
that operate on different data sets.
