Introduction
672
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Parameter Overlay Module (POM)
18.1 Introduction
In many applications it is important to be able to change certain parameters in the program without having
to re-flash the device and immediately test these changes either in a hardware-in-the-loop simulation or in
a real environment.
The POM provides a mechanism to redirect accesses to non-volatile memory into a volatile memory
internal or external to the device. The data requested by the CPU will be fetched from the overlay memory
instead of the main non-volatile memory.
18.1.1 Main Features
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Redirects program memory accesses to internal or external memory (overlay memory)
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Up to 8 MByte of external overlay memory
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Provides up to 32 programmable memory regions to replace non-volatile memory
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Programmable region start address
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Programmable region size (64 Bytes up to 256 kBytes in power of 2 steps)
18.1.2 Parameter Overlay Module (POM) Considerations
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The POM can map onto up to 8MB of the internal or external memory space. The starting address and
the size of the memory overlay are configurable through the POM control registers. Care must be
taken to ensure that the overlay is mapped on to available memory.
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ECC must be disabled by software through CP15 in case POM overlay is enabled; otherwise ECC
errors will be generated.
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POM overlay must not be enabled when the flash and internal RAM memories are swapped through
the MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).
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When POM is used to overlay the flash on to internal or external RAM, there is a bus contention
possibility when another master accesses the TCM flash. This results in a system hang.
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The POM implements a timeout feature to detect this exact scenario. The timeout needs to be
enabled whenever POM overlay is enabled.
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The timeout can be enabled by writing Ah to the enable timeout (ETO) field of the POM global
control register (POMGLBCTRL).
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In case a read request by the POM cannot be completed within 32 HCLK cycles, the timeout (TO)
flag is set in the POM status register (POMFLG). Also, an abort is generated to the CPU. This can
be a prefetch abort for an instruction fetch or a data abort for a data fetch.
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The prefetch-abort and data-abort handlers must be modified to check if the TO flag in the POM is
set. If so, then the application can assume that the timeout is caused by a bus contention between
the POM transaction and another master accessing the same memory region. The abort handlers
need to clear the TO flag, so that any further aborts are not misinterpreted as having been caused
due to a timeout from the POM.
