EMIF Module Architecture
627
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
External Memory Interface (EMIF)
17.2.5.6.1 Determining the Appropriate Value for the RR Field
The value that should be programmed into the RR field of SDRCR can be calculated by using the
frequency of the EMIF_CLK signal (f
EMIF_CLK
) and the required refresh rate of the SDRAM (f
Refresh
). The
following formula can be used:
RR = f
EMIF_CLK
/ f
Refresh
The SDRAM datasheet often communicates the required SDRAM Refresh Rate in terms of the number of
REFR commands required in a given time interval. The required SDRAM Refresh Rate in the formula
above can therefore be calculated by dividing the number of required cycles per time interval (n
cycles
) by
the time interval given in the datasheet (t
Refresh Period
) :
f
Refresh
= n
cycles
/ t
Refresh Period
Combining these formulas, the value that should be programmed into the RR field can be computed as:
RR = f
EMIF_CLK
× t
Refresh Period
/ n
cycles
The following example illustrates calculating the value of RR. Given that:
•
f
EMIF_CLK
= 100 MHz (frequency of the EMIF clock)
•
t
Refresh Period
= 64 ms (required refresh interval of the SDRAM)
•
n
cycles
= 8192 (number of cycles in a refresh interval for the SDRAM)
RR can be calculated as:
RR = 100 MHz × 64 ms/8192
RR = 781.25
RR = 782 cycles = 30Eh cycles
17.2.5.7 Self-Refresh Mode
The EMIF can be programmed to enter the self-refresh state by setting the SR bit of SDCR to 1. This will
cause the EMIF to issue the SLFR command after completing any outstanding SDRAM access requests
and clearing the refresh backlog counter by performing one or more auto refresh cycles. This places the
attached SDRAM device into self-refresh mode in which it consumes a minimal amount of power while
performing its own refresh cycles. The SR bit should be set and cleared using a byte-write to the upper
byte of the SDRAM configuration register (SDCR) to avoid triggering the SDRAM initialization sequence.
While in the self-refresh state, the EMIF continues to service asynchronous bank requests and register
accesses as normal, with one caveat. The EMIF will not park the data bus following a read to
asynchronous memory while in the self-refresh state. Instead, the EMIF tri-states the data bus. Therefore,
it is not recommended to perform asynchronous read operations while the EMIF is in the self-refresh state,
in order to prevent floating inputs on the data bus. More information about data bus parking can be found
in
.
The EMIF will exit from the self-refresh state if either of the following events occur:
•
The SR bit of SDCR is cleared to 0.
•
An SDRAM accesses is requested.
The EMIF exits from the self-refresh state by driving EMIF_CKE high and performing an auto refresh
cycle.
The attached SDRAM device should also be placed into Self-Refresh Mode when changing the frequency
of EMIF_CLK. If the frequency of EMIF_CLK changes while the SDRAM is not in Self-Refresh Mode,
Procedure B in
should be followed to reinitialize the device.
