Rev. 1.0, 02/00, page 765 of 1141
27.2.2
Sync Separation Control Register (SEPCR)
0
0
0
0
0
0
0
0
7
R
FLD
0
R/W
AFCVIE
6
R/(W)
*
AFCVIF
5
R/W
VCKSL
4
R/W
VCMPON
3
R/W
HCKSEL
2
R/W
HHKON
1
—
—
Bit :
Initial value :
R/W :
Note:
*
Only 0 can be written to clear the flag.
The SEPCR is an 8-bit read/write register for controlling the external Vsync interrupt, enabling or
disabling the V complement function, selecting the clock source for the V complement and mask
counter, selecting the clock source for the internal Csync generator, and indicating the field
detected by the AFC. When reset, the SEPCR is initialized to H'00.
Bit 7
External Vsync Interrupt Enable (AFCVIE): Enables or disables the external Vsync
interrupt to be requested when the AFCVIF is set to 1.
Bit 7
AFCVIE
Description
0
The external Vsync interrupt is disabled
(Initial value)
1
The external Vsync interrupt is enabled
Bit 6
External Vsync Interrupt Flag (AFCVIF): This flag is set to 1 when the V complement
and mask counter detects the external Vsync signal (the AFCV signal). For the Vsync interrupt
generated in the OSD, refer to section 29, On Screen Display (OSD).
Bit 6
AFCVIF
Description
0
[Clearing condition]
1 is read, then 0 is written
(Initial value)
1
[Setting condition]
The V complement and mask counter detects the external Vsync signal (AFCV
signal)