R&S ZVL
Remote Control
Status Reporting System
Operating Manual 1303.6580.32-05
339
STATus:OPERation
The STATus:OPERation register contains conditions which are part of the instrument's normal operation.
The analyzer does not use the STATus:OPERation register:
STATus:QUEStionable
The STATus:QUEStionable register indicates whether the acquired data is of questionable quality and
monitors hardware failures of the analyzer. It can be queried using the commands
STATus:QUEStionable:CONDition?
or
STATus:QUEStionable[:EVENt]?
The bits in the STATus:QUEStionable register are defined as follows:
Bit
No.
Meaning
9
Integrity Register summary
This bit is set if a bit is set in the STATus:QUEStionable:INTegrity register and the associated ENABle
bit is set to 1.
10
Limit Register summary
This bit is set if a bit is set in the STATus:QUEStionable:LIMit1 register and the associated ENABle bit is
set to 1.
STATus:QUEStionable:LIMit1<1|2>
The STATus:QUEStionable:LIMit<1|2> registers indicate the result of the limit check. They can be queried
using the commands
STATus:QUEStionable:LIMit<1|2>:CONDition?
or
STATus:QUEStionable:LIMit<1|2>[:EVENt]?
STATus:QUEStionable:LIMit1 is also the summary
register of the lower-level STATus:QUEStionable:LIMit2 register.
The bits in the STATus:QUEStionable:LIMit1 register are defined as follows:
Bit
No.
Meaning
0
LIMit2 Register summary
This bit is set if a bit is set in the STATus:QUEStionable:LIMit2 register and the associated ENABle bit
is set to 1.
1
Failed Limit Check for Trace no. 1
This bit is set if any point on trace no. 1 fails the limit check.
...
...
14
Failed Limit Check for Trace no. 14
This bit is set if any point on trace no. 14 fails the limit check.
The bits in the STATus:QUEStionable:LIMit2 register are defined as follows:
Bit No.
Meaning
0
Not used
1
Failed Limit Check for Trace no. 15
This bit is set if any point on trace no. 15 fails the limit check.
