Command Reference
R&S
®
ZNB/ZNBT
1136
User Manual 1173.9163.02 ─ 38
STATus:QUEStionable:INTegrity:HARDware[:EVENt]?
STATus:QUEStionable:LIMit<Lev>[:EVENt]?
These commands return the contents of the
EVENt
parts of the
QUEStionable
,
QUEStionable:INTegrity
,
QUEStionable:INTegrity:HARDware
, and
QUEStionable:LIMit<Lev>
status registers. Reading an
EVENt
register clears it.
Suffix:
<Lev>
.
Selects one of the two
QUEStionable:LIMit
registers; see
"STATus:QUEStionable:LIMit<1|2>"
Example:
STAT:QUES:LIM1?
Query the
EVENt
part of the
QUEStionable:LIMit1
register
to check whether an event has occurred since the last reading.
Usage:
Query only
STATus:QUEStionable:CONDition?
STATus:QUEStionable:INTegrity:CONDition?
STATus:QUEStionable:INTegrity:HARDware:CONDition?
STATus:QUEStionable:LIMit<Lev>:CONDition?
Returns the contents of the
CONDition
part of the
QUEStionable...
registers.
Reading the
CONDition
registers is nondestructive.
Suffix:
<Lev>
.
Selects one of the two
QUEStionable:LIMit
registers; see
"STATus:QUEStionable:LIMit<1|2>"
Example:
STAT:QUES:LIMit:COND?
Query the
CONDition
part of the
QUEStionable:LIMit1
reg-
ister to retrieve the current status of the limit check.
Usage:
Query only
STATus:QUEStionable:ENABle
<BitPattern>
STATus:QUEStionable:INTegrity:ENABle
<BitPattern>
STATus:QUEStionable:INTegrity:HARDware:ENABle
<BitPattern>
STATus:QUEStionable:LIMit<Lev>:ENABle
<BitPattern>
Sets the enable mask which allows true conditions in the
EVENt
part of the
QUEStionable...
registers to be reported in the summary bit. If a bit is 1 in the
enable register and its associated event bit transitions to true, a positive transition will
occur in the summary bit (e.g. bit 10 of the
QUEStionable
register for the
LIMit1
register, bit 0 of the
LIMit1
register for the
LIMit2
register).
See also
Chapter 6.5.1, "Overview of Status Registers"
ter 6.5.5, "Reset Values of the Status Reporting System"
Suffix:
<Lev>
.
Selects one of the two
QUEStionable:LIMit
registers; see
"STATus:QUEStionable:LIMit<1|2>"
SCPI Command Reference