GD32W51x User Manual
787
Bits
Identifier
Type
Value
Description
Clear
Condition
bits w as made.
15
WP_ERASE_SKIP
ERX
’0’= not protected
’1’= protected
Set w hen only partial address
space w as erased due to
existing w rite protected
blocks or the temporary or
permanent w rite protected
card w as erased.
C
14
CARD_ECC_DISABLE
D
SX
’0’= enabled
’1’= disabled
The command has been
executed w ithout using the
internal ECC.
A
13
ERASE_RESET
SR
’0’= cleared
’1’= set
An erase sequence w as
cleared before executing
because an out of erase
sequence command w as
received.
C
[12:9]
CURRENT_STATE
SX
0 = idle
1 = ready
2 = identification
3 = stand by
4 = transfer
5 = send data
6 = receive data
7 = programming
8 = disconnect
9-14 = reserved
15 = reserved for
I/O mode
The state of the card w hen
receiving the command. If the
command execution causes a
state change, it w ill be visible
to the host in the response to
the next command. The four
bits are interpreted as a
binary coded number
betw een 0 and 15.
B
8
READY_FOR_DA TA
SX
’0’= not ready
’1’= ready
Corresponds to buffer empty
signaling on the bus.
A
7
SWITCH_ERROR
EX
’0’= no error
’1’= sw itch error
If set, the card don’t sw itch to
the expected mode as
requested by the SWITCH
command.
B
6
Reserved
5
APP_CMD
SR
’0’= enabled
’1’= disabled
The card w ill expect ACMD,
or an indication that the
command has been
interpreted as ACMD.
C
4
Reserved
3
AKE_SEQ_ERROR
ER
’0’= no error
’1’= error
Only for SD memory. Error in
the sequence of the
C