GD32W51x User Manual
744
This register can be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
WSC
TMOUTC
SMC
Reserved
TCC
TERRC
w
w
w
w
w
Bits
Fields
Descriptions
31:6
Reserved
Must be kept at reset value
5
WSC
Clear w rong start sequence flag
Writing 1 clears the WS flag in the QSPI_STAT register
4
TMOUTC
Clear timeout flag
Writing 1 clears the TMOUT flag in the QSPI_STAT register
3
SMC
Clear status match flag
Writing 1 clears the SM flag in the QSPI_STAT register
2
Reserved
Must be kept at reset value
1
TCC
Clear transfer complete flag
Writing 1 clears the TC flag in the QSPI_STAT register
0
TERRC
Clear transfer error flag
Writing 1 clears the TERR flag in the QSPI_STAT register
22.11.12.
Secure Data length register (QSPI_DTLEN_SEC)
Address offset: 0x110
Reset value: 0x0000 0000
This register can be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DTLEN[31:16]
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DTLEN[15:0]
rw
Bits
Fields
Descriptions
31:0
DTLEN[31:0]
Data length
Number of data to be retrieved (value+1) in indirect and status -polling modes. A
value no greater than 3 (indicating 4 bytes) should be used for status-polling mode.
All 1s in indirect mode means undefined length, w here QSPI w ill continue until the