GD32W51x User Manual
188
1: Enabled SRAM2 clock w hen sleep mode
17
SRAM1SPEN
SRAM1 clock enable w hen sleep mode
This bit is set and reset by softw are.
0: Disabled SRAM1 clock w hen sleep mode
1: Enabled SRAM1 clock w hen sleep mode
16
SRAM0SPEN
SRAM0 clock enable w hen sleep mode
This bit is set and reset by softw are.
0: Disabled SRAM0 clock w hen sleep mode
1: Enabled SRAM0 clock w hen sleep mode
15
FMCSPEN
FMC clock enable w hen sleep mode
This bit is set and reset by softw are.
0: Disabled FMC clock w hen sleep mode
1: Enabled FMC clock w hen sleep mode
14
WIFIRUNSPEN
WIFIRUN clock enable w hen sleep mode
This bit is set and reset by softw are.
0: Disabled WIFIRUN clock w hen sleep mode
1: Enabled WIFIRUN clock w hen sleep mode
13
WIFISPEN
Wi-Fi clock enable w hen sleep mode
This bit is set and reset by softw are.
0: Disabled Wi-Fi clock w hen sleep mode
1: Enabled Wi-Fi clock w hen sleep mode
12
CRCSPEN
CRC clock enable w hen sleep mode
This bit is set and reset by softw are.
0: Disabled CRC clock w hen sleep mode
1: Enabled CRC clock w hen sleep mode
11:9
Reserved
Must be kept at reset value.
8
TSISPEN
TSI clock enable w hen sleep mode
This bit is set and reset by softw are.
0: Disabled TSI clock w hen sleep mode
1: Enabled TSI clock w hen sleep mode
7
TZGPCSPEN
TZGPC clock enable w hen sleep mode
This bit is set and reset by softw are.
0: Disabled TZGPC clock w hen sleep mode
1: Enabled TZGPC clock w hen sleep mode
6:3
Reserved
Must be kept at reset value.
2
PCSPEN
GPIO port C clock enable w hen sleep mode
This bit is set and reset by softw are.
0: Disabled GPIO port C clock w hen sleep mode