GD32W51x User Manual
1030
When the serial transceiver is not yet synchronized, the clock loss flag is set and
cannot be cleared by CKLFC[1:0].
This bit is only available in HPDF_FLT0INTC register.
15:4
Reserved
Must be kept at reset value.
3
RCDOFC
Clear the regular conversion data overflow flag
0: No effect
1: Clear the RCDOF bit in the HPDF_FLTySTAT register
2
ICDOFC
Clear the inserted conversion data overflow flag
0: No effect
1: Clear the ICDOF bit in the HPDF_FLTySTAT register
1:0
Reserved
Must be kept at reset value.
Filter y inserted channel group selection register (HPDF_FLTyICGS)
Address offset:
0x110 + 0x80 * y, (y = 0, 1)
Reset value: 0x0000 0001
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
15
4
3
2
1
0
Reserved
ICGSEL[1:0]
rw
Bits
Fields
Descriptions
31:2
Reserved
Must be kept at reset value.
1:0
ICGSEL[1:0]
Inserted channel group selection
01:
Channel 0 belongs to the inserted group
10: Channel 1 belongs to the inserted group
11:
Channel 0 and channel 1 belong to the inserted group
If SCMOD=1, each of the selected channels is converted, one after another. The
priority conversion w ith low est channel number.
If SCMOD=0, then only one channel is converted from the selected channels, and
the channel selection is moved to the next channel.
When SCMOD=0, Writing ICGSEL w ill reset the channel selection to the low est
selected channel.
At least one channel must alw ays be selected for the inserted group. All w rites that
make ICGSEL[1:0]=0 are ignored.