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GigaDevice Semiconductor GD32W515 Series, User Manual

The GigaDevice Semiconductor GD32W515 Series is a versatile and high-performance microcontroller designed for hardware development projects. Its comprehensive Hardware Development Manual is available for free download, providing enthusiasts with detailed instructions and insights. Unlock the full potential of this exceptional product by downloading the manual from manualshive.com.

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GD32W51x User Manual

 

470 

 

 

 

Mode Selection 

Source Selection 

Polarity Selection 

Filter and Prescaler 

Exam 3 

Event m ode  

The  counter w ill start 

to count w hen a rising 

edge of trigger input 

comes. 

TRGS[2:0]  =3’b111 

ETIFP  is selected. 

ETP  = 0, the polarity 

of ETI  does not 

change. 

ETPSC  = 1, ETI  is 

divided  by 2. 

ETFC  = 0, ETI  does 

not filter. 

Figure 17-26. Event m ode  

 

 

TIMER_CK

CNT_REG

5E

5F

60

61

ETI

TRGIF

ETIFP

 

Single pulse mode 

Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM 
in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update 
event automatically. In order to get pulse waveform, you can set the TIMERx to PWM mode 
or compare by CHxCOMCTL.  

Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer 
enable bit CEN  in the TIMERx_CTL0 register to 1  to enable the  counter. The  trigger to 
generate a pulse can be sourced from the trigger signals edge or by setting the CEN bit to 1 
using software. Setting the CEN bit to 1 or a trigger from the trigger signals edge can generate 
a pulse and then keep the CEN bit at a high state until the update event occurs or the CEN 
bit is written to 0 by software. If the CEN bit is cleared to 0 using software, the counter will be 
stopped and its value held. If the CEN bit is automatically cleared to 0 by a hardware update 
event, the counter will be reinitialized. 

In the single pulse mode, the trigger active edge which sets the CEN bit to 1 will enable the 
counter. However, there exist several clock delays to perform the comparison result between 
the counter value and the TIMERx_CHxCV value. In order to reduce the delay to a minimum 
value, the user can set the CHxCOMFEN bit in each TIMERx_CHCTL0/1 register. After a 
trigger rising occurs in the single pulse mode, the OxCPRE signal will immediately be forced 
to the state which the OxCPRE signal will change to, as the compare match event occurs 
without taking the comparison result into account. The CHxCOMFEN bit is available only 
when the output channel is configured to operate in the PWM0 or PWM1 output mode and 
the trigger source is derived from the trigger signal. 

Summary of Contents for GD32W515 Series

Page 1: ...GigaDevice Semiconductor Inc GD32W51x Arm Cortex M33 32 bit MCU User Manual Revision 1 0 Nov 2021 ...

Page 2: ... On chip flash memory overview 48 1 5 Boot configuration 48 1 6 System configuration controller SYSCFG 51 1 6 1 SYSCFG main features 51 1 6 2 SYSCFG TrustZone security and privilege 51 1 6 3 SYSCFG registers 52 1 7 Device electronic signature 64 1 7 1 Memory density information 64 1 7 2 Unique device ID 96 bits 65 2 Flash memory controller FMC 67 2 1 Overview 67 2 2 Characteristics 67 2 3 System o...

Page 3: ...0 93 2 5 14 Secure dedicated mark protection register 0 FMC_DMP0 94 2 5 15 Option byte write protection area register 0 FMC_OBWRP0 94 2 5 16 Secure mark configuration register 1 FMC_SECMCFG1 95 2 5 17 Secure dedicated mark protection register 1 FMC_DMP1 96 2 5 18 Option byte write protection area register 1 FMC_OBWRP1 96 2 5 19 Secure mark configuration register 2 FMC_SECMCFG2 97 2 5 20 Secure mar...

Page 4: ..._DATA 116 3 5 16 EFUSE Pre TrustZone enable register EFUSE_PRE_TZEN 117 3 5 17 TrustZone boot address register EFUSE_TZ_BOOT_ADDR 117 3 5 18 No TrustZone boot address register EFUSE_NTZ_BOOT_ADDR 118 4 Instruction cache ICACHE 119 4 1 Introduction 119 4 2 Characteristics 119 4 3 Function overview 119 4 3 1 ICACHE initialization 120 4 3 2 Paired master cache 120 4 3 3 ICACHE TAG memory 121 4 3 4 Ad...

Page 5: ...unit CCTL 153 6 2 1 Overview 153 6 2 2 Characteristics 155 6 2 3 Function overview 156 6 3 RCU security protection 159 6 4 RCU privilege protection 161 6 5 Register definition 163 6 5 1 Control register RCU_CTL 163 6 5 2 PLL register RCU_PLL 166 6 5 3 Clock configuration register 0 RCU_CFG0 167 6 5 4 Clock interrupt register RCU_INT 170 6 5 5 AHB1 reset register RCU_AHB1RST 173 6 5 6 AHB2 reset re...

Page 6: ...ction status register RCU_APB1SECP_STAT 210 6 5 32 APB2 secure protection status register RCU_APB2SECP_STAT 212 6 5 33 Voltagekey register RCU_VKEY 214 6 5 34 Deep sleep mode voltage register RCU_DSV 214 7 Interrupt event controller EXTI 216 7 1 Overview 216 7 2 Characteristics 216 7 3 Interrupts function overview 216 7 4 External interrupt and event EXTI block diagram 220 7 5 External interrupt a...

Page 7: ...t bit operate register GPIOx_BOP x A C 246 8 5 8 Port configuration lock register GPIOx_LOCK x A C 246 8 5 9 Alternate function selected register 0 GPIOx_AFSEL0 x A C 247 8 5 10 Alternate function selected register 1 GPIOx_AFSEL1 x A C 248 8 5 11 Bit clear register GPIOx_BC x A C 250 8 5 12 Port bit toggle register GPIOx_TG x A C 250 8 5 13 GPIO secure configuration register GPIOx_SCFG x A C 251 9...

Page 8: ...gisters definition 277 9 6 1 TZBMPC1 control register TZPCU_TZBMPC1_CTL 277 9 6 2 TZBMPC1 vector register y TZPCU_TZBMPC1_VECy 278 9 6 3 TZBMPC1 lock register 0 TZPCU_TZBMPC1_LOCK0 279 9 7 TZBMPC2 registers definition 279 9 7 1 TZBMPC2 control register TZPCU_TZBMPC2_CTL 279 9 7 2 TZBMPC2 vector register y TZPCU_TZBMPC2_VECy 280 9 7 3 TZBMPC2 lock register 0 TZPCU_TZBMPC2_LOCK0 281 9 8 TZBMPC3 regi...

Page 9: ...AT 312 11 4 3 Data register TRNG_DATA 313 12 Direct memory access controller DMA 315 12 1 Overview 315 12 2 Characteristics 315 12 3 Block diagram 316 12 4 Function overview 317 12 4 1 Secure priviledge 318 12 4 2 Peripheral handshake 319 12 4 3 Data process 321 12 4 4 Address generation 327 12 4 5 Circular mode 327 12 4 6 Switch buffer mode 328 12 4 7 Transfer flow controller 328 12 4 8 Transfer ...

Page 10: ...ction description 351 13 2 1 Switch JTAG or SW interface 351 13 2 2 Pin assignment 351 13 2 3 JTAG daisy chained structure 352 13 2 4 Debug reset 352 13 2 5 JEDEC 106 ID code 352 13 3 Debug hold function description 352 13 3 1 Debug support for power saving mode 352 13 3 2 Debug support for TIMER I2C WWDGT FWDGT and RTC 353 13 4 DBG registers 354 13 4 1 ID code register DBG_ID 354 13 4 2 Control r...

Page 11: ...WDLT 380 14 5 9 Regular sequence register 0 ADC_RSQ0 381 14 5 10 Regular sequence register 1 ADC_RSQ1 381 14 5 11 Regular sequence register 2 ADC_RSQ2 382 14 5 12 Inserted sequence register ADC_ISQ 383 14 5 13 Inserted data register x ADC_IDATAx x 0 3 383 14 5 14 Regular data register ADC_RDATA 384 14 5 15 Oversampling control register ADC_OVSAMPCTL 384 14 5 16 Commom control register ADC_CCTL 386...

Page 12: ...ister RTC_CTL 420 16 4 4 Initialization control andstatus register RTC_ICSR 423 16 4 5 Prescaler register RTC_PSC 424 16 4 6 Wakeup timer register RTC_WUT 425 16 4 7 Coarse calibration register RTC_COSC 425 16 4 8 Alarm 0 time and date register RTC_ALRM0TD 426 16 4 9 Alarm 1 time and date register RTC_ALRM1TD 427 16 4 10 Write protection key register RTC_WPK 429 16 4 11 Sub second register RTC_SS ...

Page 13: ...2 3 4 523 17 3 General level4 timer TIMERx x 15 16 549 17 3 1 Overview 549 17 3 2 Characteristics 549 17 3 3 Block diagram 549 17 3 4 Function overview 550 17 3 5 TIMERx registers x 15 16 564 17 4 Basic timer TIMERx x 5 580 17 4 1 Overview 580 17 4 2 Characteristics 580 17 4 3 Block diagram 580 17 4 4 Function overview 580 17 4 5 TIMERx registers x 5 584 18 Universal synchronous asynchronous recei...

Page 14: ...and register USART_CMD 618 18 4 8 Status register USART_STAT 619 18 4 9 Interrupt status clear register USART_INTC 623 18 4 10 Receive data register USART_RDATA 624 18 4 11 Transmit data register USART_TDATA 625 18 4 12 USART coherencecontrol register USART_CHC 625 18 4 13 USART receive FIFO control and status register USART_RFCS 626 19 Inter integrated circuit interface I2C 628 19 1 Overview 628 ...

Page 15: ...terface Inter IC sound SPI I2S 670 20 1 Overview 670 20 2 Characteristics 670 20 2 1 SPI characteristics 670 20 2 2 I2S characteristics 670 20 3 SPI block diagram 671 20 4 SPI signal description 671 20 4 1 Normal configuration Not Quad SPI Mode 671 20 4 2 Quad SPI configuration 672 20 5 SPI function overview 672 20 5 1 SPI clock timing and data format 672 20 5 2 NSS function 673 20 5 3 SPI operati...

Page 16: ... mode definition 711 21 3 2 SQPI controllersampling polarity 712 21 3 3 SQPI controllerspecial command 713 21 3 4 SQPI controller read ID command 713 21 3 5 SQPI controller output clock configuration 714 21 3 6 SQPI controller initialization 714 21 3 7 Read ID command flow 714 21 3 8 Read Write operation flow 714 21 3 9 SQPI controller mode timing 714 21 4 Register definition 716 21 4 1 SQPI Initi...

Page 17: ...1 22 11 10 Secure Status register QSPI_STAT_SEC 742 22 11 11 Secure Status clear register QSPI_STATC_SEC 743 22 11 12 Secure Data length register QSPI_DTLEN_SEC 744 22 11 13 Secure Transfer configuration register QSPI_TCFG_SEC 745 22 11 14 Secure Address register QSPI_ADDR_SEC 747 22 11 15 Secure Alternate bytes register QSPI_ALTE_SEC 747 22 11 16 Secure Data register QSPI_DATA_SEC 748 22 11 17 St...

Page 18: ... 794 23 6 4 Single block or multiple block read 795 23 6 5 Stream write and stream read MMC only 796 23 6 6 Erase 798 23 6 7 Bus width selection 799 23 6 8 Protection management 799 23 6 9 Card Lock Unlock operation 799 23 7 Specific operations 802 23 7 1 SD I Ospecific operations 802 23 7 2 CE ATA specific operations 805 23 8 SDIO registers 807 23 8 1 Power control register SDIO_PWRCTL 807 23 8 2...

Page 19: ...rupts 835 24 7 Register definition 837 24 7 1 Global control and status registers 837 24 7 2 Host control and status registers 858 24 7 3 Device control andstatus registers 870 24 7 4 Power andclock control register USBFS_PWRCLKCTL 894 25 Digital camera interface DCI 895 25 1 Overview 895 25 2 Characteristics 895 25 3 Block diagram 895 25 4 Signal description 896 25 5 Function overview 896 25 5 1 ...

Page 20: ...s 913 26 3 6 PIN modecontrol of TSI 914 26 3 7 Analog switch ASW and I O hysteresis mode 914 26 3 8 TSI operation flow 915 26 3 9 TSI flags and interrupts 915 26 3 10 TSI GPIOs 915 26 4 Registers definition 916 26 4 1 Control register0 TSI_CTL0 916 26 4 2 Interrupt enable register TSI_INTEN 918 26 4 3 Interrupt flag clear register TSI_INTC 919 26 4 4 Interrupt flag register TSI_INTF 919 26 4 5 Pin...

Page 21: ...ter CAU_INTF 948 27 9 9 Key registers CAU_KEY0 3 H L 949 27 9 10 Initial vector registers CAU_IV0 1 H L 951 27 9 11 GCM or CCM mode context switch register x CAU_GCMCCMCTXSx x 0 7 953 27 9 12 GCM mode context switch register x CAU_GCMCTXSx x 0 7 953 28 Hash Acceleration Unit HAU 954 28 1 Overview 954 28 2 Characteristics 954 28 3 HAU data type 954 28 4 HAU core 956 28 4 1 Automatic data padding 95...

Page 22: ... errors and interrupts 990 29 4 Register definition 992 29 4 1 Control register PKCAU_CTL 992 29 4 2 Status register PKCAU_STAT 993 29 4 3 Status clear register PKCAU_STATC 994 30 High Performance Digital Filter HPDF 996 30 1 Overview 996 30 2 Characteristics 996 30 3 Function overview 996 30 3 1 HPDF Block Diagram 996 30 3 2 HPDF on off control 997 30 3 3 HPDF clock 998 30 3 4 Multiplex serial da...

Page 23: ...31 3 Function overview 1038 32 Wi Fi 1040 32 1 Overview 1040 32 2 Characteristics 1040 32 2 1 Standards Supported 1040 32 2 2 Wi Fi MAC 1040 32 2 3 Wi Fi PHY 1040 32 2 4 Wi Fi Radio 1041 33 Document appendix 1042 33 1 List of abbreviations used in registers 1042 33 2 List of terms 1042 33 3 Available peripherals 1042 34 Revision history 1043 ...

Page 24: ...Figure 8 1 Basic structure of a standard I O port bit 232 Figure 8 2 Input configuration 233 Figure 8 3 Output configuration 234 Figure 8 4 Analog configuration 235 Figure 8 5 Alternate function configuration 235 Figure 9 1 Block diagram of TZPCU 252 Figure 10 1 Block diagram of CRC calculation unit 306 Figure 11 1 TRNG block diagram 310 Figure 12 1 Block diagram of DMA 316 Figure 12 2 Data stream...

Page 25: ... counting mode 455 Figure 17 11 Repetition counter timing chart of down counting mode 456 Figure 17 12 Input capture logic 457 Figure 17 13 Output compare logic with complementary output x 0 1 2 458 Figure 17 14 Output compare logic CH3_O 458 Figure 17 15 Output compare in three modes 460 Figure 17 16 Timing chart of EAPWM 461 Figure 17 17 Timing chart of CAPWM 461 Figure 17 18 Complementary outpu...

Page 26: ...Figure 17 55 Counter timing diagram with prescaler division change from 1 to 2 551 Figure 17 56 Up counter timechart PSC 0 1 552 Figure 17 57 Up counter timechart change TIMERx_CAR on the go 553 Figure 17 58 Repetition timechart for up counter 554 Figure 17 59 Input capture logic 555 Figure 17 60 Output compare logic with complementary output x 0 556 Figure 17 61 Output compare under three modes 5...

Page 27: ... 636 Figure 19 12 Data reception 636 Figure 19 13 I2C initialization in slave mode 640 Figure 19 14 Programming model for slave transmitting when SS 0 641 Figure 19 15 Programming model for slave transmitting when SS 1 642 Figure 19 16 Programming model for slave receiving 643 Figure 19 17 I2C initialization in master mode 644 Figure 19 18 Programming model for master transmitting N 255 645 Figure...

Page 28: ...ram DTLEN 01 CHLEN 1 CKPL 1 688 Figure 20 28 MSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 0 688 Figure 20 29 MSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 1 689 Figure 20 30 LSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 0 689 Figure 20 31 LSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 689 Figure 20 32 LSB justified standard timing diagram D...

Page 29: ...Q Mode Timing SQPI 715 Figure 21 8 SQPI QQQ Mode Timing QPI 716 Figure 21 9 SQPI SSD Mode Timing 716 Figure 21 10 SQPI SDD Mode Timing 716 Figure 22 1 QSPI diagram 722 Figure 22 2 QSPI command format 723 Figure 22 3 CSN and SCK behavior 726 Figure 23 1 SDIO no response and no data operations 759 Figure 23 2 SDIO multiple blocks read operation 760 Figure 23 3 SDIO multiple blocks write operation 76...

Page 30: ...ing 926 Figure 27 2 DATAM Byte swapping and Bit swapping 927 Figure 27 3 CAU diagram 928 Figure 27 4 DES TDES ECB encryption 929 Figure 27 5 DES TDES ECB decryption 930 Figure 27 6 DES TDES CBC encryption 931 Figure 27 7 DES TDES CBC decryption 932 Figure 27 8 AES ECB encryption 933 Figure 27 9 AES ECB decryption 933 Figure 27 10 AES CBC encryption 934 Figure 27 11 AES CBC decryption 935 Figure 27...

Page 31: ...calar multiplication of fast mode 984 Figure 29 22 ECDSA sign 986 Figure 29 23 ECDSA verification 987 Figure 30 1 HPDF block diagram 997 Figure 30 2 The sequence diagram of SPI data transmission 1000 Figure 30 3 The sequence diagram of Manchester data transmission 1001 Figure 30 4 Manchester synchronous sequence diagram 1002 Figure 30 5 Clock loss detection timing diagram 1003 Figure 30 6 Channel ...

Page 32: ...operation under different protection levels when TrustZone is disable TZEN 0 80 Table 2 7 Flash mass erase operation under different protection levels when TrustZone is active TZEN 1 81 Table 2 8 Flash interrupt requests non secure 82 Table 2 9 Flash interrupt requests secure 83 Table 3 1 EFUSE address mapping 103 Table 3 2 system parameters 104 Table 4 1 TAG memory parameters 121 Table 4 2 ICAHCE...

Page 33: ...er modes 367 Table 14 4 External trigger for regular channels of ADC 368 Table 14 5 External trigger for inserted channels of ADC 368 Table 14 6 Maximum output results for N and M combimations grayed values indicates truncation 371 Table 15 1 Min max FWDGT timeout period at 32 kHz IRC32K 388 Table 15 2 Min max timeout value at 45 MHz fPCLK1 395 Table 16 1 RTC register secure access rules 411 Table...

Page 34: ... 1 SQPI controller mode definition 711 Table 22 1 QSPI signal description 722 Table 22 2 QSPI singnal line modes 724 Table 22 3 Flash secure non secure and privileged unprivileged operation under FMC mode when TrustZone is active TZEN 1 729 Table 22 4 QSPI interrupt requests 731 Table 23 1 SDIO I O definitions 762 Table 23 2 Command format 768 Table 23 3 Card command classes CCCs 769 Table 23 4 Ba...

Page 35: ... and flags 915 Table 26 5 TSI pins 915 Table 29 1 Parameters of RSA algorithm 970 Table 29 2 Integer arithmetic operations 972 Table 29 3 Range of parameters used by RSA CRT exponentiation operation 982 Table 29 4 Elliptic curve operations in Fp domain 982 Table 29 5 Range of parameters used by point on elliptic curve Fp check 983 Table 29 6 Range of parameters used by ECC scalar multiplication 98...

Page 36: ...nd IOR SFOR SFO of the integrator 1010 Table 30 7 Features of threshold monitor working mode 1011 Table 30 8 Maximum output rate 1014 Table 30 9 HPDF interrupt event 1015 Table 33 1 List of abbreviations used in register 1042 Table 33 2 List of terms 1042 Table 34 1 Revision history 1043 ...

Page 37: ...rformance and lowpower consumption TheCortex M33processoris basedontheARMv8architecture and supports a powerful and scalable instruction set includinggeneral data processing I O control tasks advanced data processing bit field manipulations and DSP Some system peripherals listed below are also provided by Cortex M33 Internal Bus Matrix connected with Code bus System bus and Private Peripheral Bus ...

Page 38: ...ce AHB Lite Code interface Serial Wire or JTAG Debug Interface PPB APB Debug system interface DSP Extension 1 2 System architecture A 32 bit multilayer bus is implemented in the GD32W51x devices which enables parallel access pathsbetweenmultiplemastersandslaves inthesystem Themultilayerbus consists of an AHB interconnect matrix three AHB buses and two APB buses The interconnection relationshipofth...

Page 39: ...rm transfer to from memories and the targets of DMA0M bus are internal Flash internal SRAMs and external memories QSPI_flash and SQPI_PSRAM the target s of DMA1M bus are internal Flash internal SRAMs external memories QSPI_flash and SQPI_PSRAM and the AHB APB peripherals DMA0P and DMA1P are the peripheral buses of DMA0 and DMA1 respectively which is used by the DMA to access AHB APB peripherals or...

Page 40: ...ge Slave AHB1 Fmax 180MHz GP DMA0 8 chs M P GP DMA1 8 chs M P Master Master Flash Memory CRC EFUSE Slave AHB2 Fmax 180MHz DCI CAU HAU TRNG PKCAU Slave AHB3 Fmax 180MHz QSPI SQPI TZWMMPC1 TZWMMPC2 Slave SDIO HPDF USART2 SPI0 ADC EXTI 1 3 TrustZone overview 1 3 1 TrustZone security attribution The security architecture is based on Arm TrustZone with the ARMv8 M Main Extension The TrustZone security ...

Page 41: ...M space is not aliased Figure 1 3 Example of memory map security attribution vs SAU configuration regions NS 0x0000 0000 NS 0x0800 0000 NSC 0x0C00 0000 NS 0x1000 0000 NS 0x2000 0000 NSC 0x3000 0000 NS 0x4000 0000 NSC 0x5000 0000 NS 0x6000 0000 0xDFFF FFFF Code external memories Code Flash and SRAM Code external memories SRAM Peripherals External memories IDAU security attribution S or NS or NSC NS...

Page 42: ...heral classification When the TrustZone security is active a peripheral can be securable secure non secure or TrustZone aware type For securable peripherals by TZSPC TrustZone security controller theSECsecurity bit correspondingtothis peripheral is set intheTZSPC_SAM_CFGx register For securable peripherals by TZSPC TrustZone security controller the SEC security bit corresponding to this peripheral...

Page 43: ...R16 Wi Fi_RF SDIO HPDF Table 1 4 TrustZone aware peripherals BUS Peripheral AHB1 DMA0 DMA1 RCU FMC GPIOA GPIOB GPIOC TZSPC AHB3 QSPI_FLASH APB1 RTC PMU APB2 EXTI SYSCFG 1 4 Memory map The Arm Cortex M33 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load store data Program memory data memory ...

Page 44: ... MEM Peripheral AHB2 0x5C06 3000 0x5FFF FFFF 0x4C06 3000 0x4FFF FFFF Reserv ed 0x5C06 1000 0x5C06 2FFF 0x4C06 1000 0x4C06 2FFF PKCAU 0x5C06 0C00 0x5C06 0FFF 0x4C06 0C00 0x4C06 0FFF Reserv ed 0x5C06 0800 0x5C06 0BFF 0x4C06 0800 0x4C06 0BFF TRNG 0x5C06 0400 0x5C06 07FF 0x4C06 0400 0x4C06 07FF HAU 0x5C06 0000 0x5C06 03FF 0x4C06 0000 0x4C06 03FF CAU 0x5C05 0400 0x5C05 FFFF 0x4C05 0400 0x4C05 FFFF Rese...

Page 45: ...5002 2FFF 0x4002 2C00 0x4002 2FFF Reserv ed 0x5002 2800 0x5002 2BFF 0x4002 2800 0x4002 2BFF EFUSE 0x5002 2400 0x5002 27FF 0x4002 2400 0x4002 27FF Reserv ed 0x5002 2000 0x5002 23FF 0x4002 2000 0x4002 23FF FMC 0x5002 1C00 0x5002 1FFF 0x4002 1C00 0x4002 1FFF Reserv ed 0x5002 1800 0x5002 1BFF 0x4002 1800 0x4002 1BFF Reserv ed 0x5002 1400 0x5002 17FF 0x4002 1400 0x4002 17FF Reserv ed 0x5002 1000 0x5002...

Page 46: ... 7000 0x5000 73FF 0x4000 7000 0x4000 73FF PMU 0x5000 6C00 0x5000 6FFF 0x4000 6C00 0x4000 6FFF Reserv ed 0x5000 5C00 0x5000 6BFF 0x4000 5C00 0x4000 6BFF Reserv ed 0x5000 5800 0x5000 5BFF 0x4000 5800 0x4000 5BFF I2C1 0x5000 5400 0x5000 57FF 0x4000 5400 0x4000 57FF I2C0 0x5000 4C00 0x5000 53FF 0x4000 4C00 0x4000 53FF Reserv ed 0x5000 4800 0x5000 4BFF 0x4000 4800 0x4000 4BFF USART0 0x5000 4400 0x5000 ...

Page 47: ... 0x0E02 0000 0x0E03 FFFF 0x0A02 0000 0x0A03 FFFF SRAM2 128KB 0x0E01 0000 0x0E01 FFFF 0x0A01 0000 0x0A01 FFFF SRAM1 64KB 0x0E00 0000 0x0E00 FFFF 0x0A00 0000 0x0A00 FFFF SRAM0 64KB 0x0C20 0000 0x0DFF FFFF 0x0820 0000 0x09FF FFFF Reserv ed 0x0C00 0000 0x0C1F FFFF 0x0800 0000 0x081F FFFF Flash memory 0x0000 0000 0x07FF FFFF External memories remap 1 4 1 On chip SRAM memory The GD32W51x series of devic...

Page 48: ...tion or setting the BKERASE bit in the RTC_TAMP register 1 4 5 On chip flash memory overview The devices provide up to 2048 KB of on chip flash memory and the flash memory organized into 512 pages with 4 KB and 256KB information block for the boot loader Refer to Flash memory controller FMC Chapter for more details 1 5 Boot configuration At startup a BOOT0 pin a BOOT1 pin are used to select the bo...

Page 49: ...FBOOTLK BOOT0 BOOT1 Boot address Boot area 0 0 0x08000000 SIP Flash w hen cfg_qspi is 0 QSPI Flash w hen cfg_qspi is 1 0 1 0 0x0BF40000 Bootloader ROM 0 1 1 0x0A000000 SRAM0 1 0 0x08000000 SIP Flash w hen cfg_qspi is 0 QSPI Flash w hen cfg_qspi is 1 1 1 0x0BF40000 Bootloader ROM When TrustZone is enabled by setting the TZEN option bit the boot space must be in secure area Table 1 9 Boot modeswhen ...

Page 50: ... the user to set BOOTx values to select the required boot mode The BOOTx pin or EFBOOTx bit depending on the EFBOOTLK and SWBOOTx bit value in the EFUSE_CTL register is also re sampled when exiting from Standby mode Consequently they must be kept in the required Boot mode configuration in Standby mode After startup delay the selection of the boot area is done before releasing the processor reset T...

Page 51: ...hen the TrustZone security is activated the SYSCFGis able to secure registers from being modified by non secure accesses The TrustZone security is activated by the TZEN option bit in the EFUSE_TZCTL register or the TZEN option bit in the option byte A non secure read write access to a secured register is RAZ WI and generates an illegal access event An illegal access interrupt is generated if the S...

Page 52: ...escriptions 31 2 Reserved Must be kept at reset value 1 0 BOOT_MODE 1 0 Boot mode Refer to Boot configuration for details Bit0 is mapping to the BOOT0 value the value of bit1 is the opposite of the BOOT1_n option bit value x0 Boot from the others 01 Refer to Boot configuration for details 11 Boot from the embedded SRAM EXTI sources selection register 0 SYSCFG_EXTISS0 Address offset 0x08 Reset valu...

Page 53: ...3 0 EXTI 0 sources selection 0000 PA0 pin 0001 PB0 pin 0010 PC0 pin Other configurations are reserved EXTI sources selection register 1 SYSCFG_EXTISS1 Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI7_SS 3 0 EXTI6_SS 3 0 EXTI5_SS 3 0 EXTI4_SS 3 0 rw rw rw r...

Page 54: ...SYSCFG_EXTISS2 Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI11_SS 3 0 EXTI10_SS 3 0 EXTI9_SS 3 0 EXTI8_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 EXTI11_SS 3 0 EXTI 11 sources selection 0000 PA11 pin 0001...

Page 55: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI15_SS 3 0 EXTI14_SS 3 0 EXTI13_SS 3 0 EXTI12_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 EXTI15_SS 3 0 EXTI 15 sources selection 0000 PA15 pin 0001 PB15 pin Other configurations are reserved 11 8 EXTI14_SS 3 0 EXTI 14 sources selection 0000 PA14 pin 0001 PB14 pin Other configurations are reserved 7 4 EXTI13_SS 3 0 ...

Page 56: ...ation cell pow er dow n 0 I O compensation cell pow er dow n mode 1 I O compensation cell enabled SYSCFG secure configuration register SYSCFG_SECFG Address offset 0x40 Reset value 0x0000 0000 When the system is secure TZEN 1 this register provides write and read access security only when the access is secure A non secure write or read access is RAZ WI and generates an illegal access event When the...

Page 57: ...ecurity 0 SYSCFG configuration clock in RCU registers can be w ritten by secure and non secure access 1 SYSCFG configuration clock in RCU registers can be w ritten by secure access only FPU interrupt enable register SYSCFG_FPUINTEN Address offset 0x48 Reset value 0x0000 001F When the system is secure TZEN 1 this register can be protected against non secure access by setting the FPUSE bit in the SY...

Page 58: ...de by 0 interrupt enable 0 IOPIZ Invalid operation interrupt enable bit 0 Invalid operation interrupt disable 1 Invalid operation interrupt enable SYSCFG CPU non secure lock register SYSCFG_CNSLOCK Address offset 0x4C Reset value 0x0000 0000 This register is used to lock the configuration of non secure MPU and VTOR_NS registers When the system is secure TZEN 1 read write access is no access restri...

Page 59: ...onfiguration of PRIS and BFHFNMINS bits in the AIRCR register SAU secure MPU and VTOR_S registers When the system is secure TZEN 1 this register can be written only when the access is secure A non secure read write access is RAZ WI and generates an illegal access event When the system is not secure TZEN 0 this register is RAZ WI This register can be read and written by privileged access only Unpri...

Page 60: ...on register 1 SYSCFG_CFG1 Address offset 0x54 Reset value 0x0000 0000 When the system is secure TZEN 1 this register can be protected against non secure access by settingthe CLASSBSE bit in theSYSCFG_SECFG register When CLASSBSE bit is set only secure access is allowed A non secure read write access is RAZ WI and generates an illegal access event When the system is not secure TZEN 0 there is no ac...

Page 61: ...SCFG_SCS Address offset 0x58 Reset value 0x0000 0000 When the system is secure TZEN 1 this register can be protected against non secure access by settingthe SRAM1SE bit in the SYSCFG_SECFG register When SRAM1SE bit is set only secure access is allowed A non secure read write access is RAZ WI and generates an illegal access event When the system is not secure TZEN 0 there is no access restriction T...

Page 62: ... be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved KEY 7 0 W Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 KEY 7 0 SRAM1 w rite protection key for softw are erase The follow ing steps are required to unlock the w rite protection of the SRAM1ERS bit in the SYSCFG_SCS register 1 Write 0xCA into ...

Page 63: ... is secure TZEN 1 this register can be protected against non secure access by settingtheSRAM1SECbitintheSYSCFG_SECCFGRregister WhenSRAM1SEC bit is set only secure access is allowed A non secure read write access is RAZ WI and generates an illegal access event When the system is not secure TZEN 0 there is no access restriction This register can be read and written by privileged and unprivileged acc...

Page 64: ...0 9 8 7 6 5 4 3 2 1 0 Reserved GSSACMD rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 GSSACMD GSSA commands Defines a command to be executed by the GSSA 1 7 Device electronic signature The device electronic signature contains memory size information and the 96 bit unique device ID It is stored in the information block of the Flash memory The 96 bit unique device ID is un...

Page 65: ... 25 24 23 22 21 20 19 18 17 16 UNIQUE_ID 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNIQUE_ID 15 0 r Bits Fields Descriptions 31 0 UNIQUE_ID 31 0 Unique device ID Base address 0x1FFF F7EC The value is factory programmed and can never be altered by user 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNIQUE_ID 63 48 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNIQUE_ID 47 32 r Bits Fields Descriptio...

Page 66: ...GD32W51x User Manual 66 Bits Fields Descriptions 31 0 UNIQUE_ID 95 64 Unique device ID ...

Page 67: ...program and read EFUSE store AES key and initial registers Word programming page erase and mass erase operation for FMC mode Security protection for FMC mode QSPI mode to prevent illegal code data access Page erase program protection to prevent unexpectedoperation for FMC mode 2 3 System overview The figure Figure2 1 FMCbusin GD32W51xshows thelocationofFMCbus inthesystem In FMCmode FMCsupports CBU...

Page 68: ... consists of 2MB main flash organized into 512 pages with 4 KB and 256KB information block for the boot loader Each page can be erased individually The structure of EXT flash depends on the specifics of the external flash The following table shows the details of flash organization in FMC mode Table 2 1 GD32W51x base addressand size for flash memory FMC mode Block Name Address range size bytes Main...

Page 69: ...the TZEN bit is reset user can choose to boot from this area 4 When the TZEN bit is set user can choose to boot from this area Select secure boot or GSSA please refer to Boot configuration 5 When the TZEN bit is set or reset secure region 2 can be accessed by other bootloaders but booting from this area is not supported 6 The bootloader block cannot be programmed or erased by user 2 4 2 Read opera...

Page 70: ...r specific settings of secure mark please refer to TrustZone security protection Note 1 Adding offset area does not support configure into NO RTDEC area 2 The offset function only supports read operation not support program operation and erase operation 2 4 3 Unlock the FMC_CTL FMC_SECCTL register After reset the FMC_CTL FMC_SECCTL register is not accessible in write mode and the LK SECLK bit in t...

Page 71: ...egisters Send the page erase command to the FMC by setting the START SECSTART bit in the FMC_CTL FMC_SECCTL register Wait until all the operations have finished by checking the value of the BUSY SE CBUSY bit in the FMC_STAT FMC_SECSTAT register Read and verify the page using a DBUS access if required When the operation is executed successfully the ENDF SECENDF bit in the FMC_STAT FMC_SECSTAT regis...

Page 72: ...n secure registers This erase can affect entire Flash block by setting the MER SECMER bit to 1 in the FMC_CTL FMC_SECCTL register The following steps show the mass erase register access sequence Unlock the FMC_CTL FMC_SECCTL register if necessary Check the BUSY SECBUSY bit in the FMC_STAT FMC_SECSTAT register to confirm that noFlashmemory operationis inprogress BUSY SECBUSYequals to0 Otherwise wai...

Page 73: ...sters directly Additionally themass eraseoperationwill beignoredif any page is erase program protected In this condition a Flash operation error interrupt will be triggered by the FMC if the ERRIE SECERRIE bit in the FMC_CTL FMC_SECCTL register is set The software can check the WPERR SECWPERR bit in the FMC_STAT FMC_SECSTAT register to detect this condition in the interrupt handler The followingfi...

Page 74: ...egister Read and verify the Flash memory using a DBUS access if required When the operation is executed successfully the ENDF SECENDF bit in the FMC_STAT FMC_SECSTAT register is set and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL FMC_SECCTL register is set Note that there are some program errors need caution Each word can be programmed only one time after erase and before...

Page 75: ...rammed and the data in Flash 3 In order to achieve the fastest programming speed user need to follow the following points when programming 1 32 bit program and the address is continuous 2 Program continuously on thebus there must be no read Flash between two write operation 3 The interval between two write operations cannot exceed 64xThclk Flash clock is hclk 2 2 4 7 Option bytes Option bytes desc...

Page 76: ... method of operating registers Option bytes modify To modify the user options value follow the procedure below Unlock the FMC_CTL FMC_SECCTL register if necessary Check the BUSY SECBUSY bit in the FMC_STAT FMC_SECSTAT register to confirm that no flash memory operation is in progress BUSY SECBUSY equals to 0 Unlock the option bytes operation bits in the FMC_CTL register if necessary Wait until the ...

Page 77: ...etting the TZEN bit in EFUSE_TZCTL register When the TrustZone is active TZEN 1 additional security features are available 4 secure mark registers define SIP Flash secure areas DMP register defines secure dedicated mark protection areas An additional security protection level protection level 0 5 Erase or program operation can be performed in secure or non secure mode with associated configuration...

Page 78: ... protection function to prevent illegal code data access to the Flash memory This function is useful for protecting the software firmware from illegal users Note FMC mode and QSPI mode implements the same security protection strategy No protection If there are option bytes when SPC 7 0 bits in FMC_OBR is set to 0xAA after the system is reset the Flash memory will be in no protection state If there...

Page 79: ...sh or backup registers or SRAM1 or RTDEC area can result in bus errors and Hard Fault interrupt When the security protection level is set to level 1and debug access is detected an intrusion will be detected When booting from GSSA the debug access is disabled When TrustZone is enabled it is no longer be able to boot from SRAM When TrustZone is disabled TZEN 0 Flash backupregisters andSRAM1arecomple...

Page 80: ...IS 1 Bus error all read data is 0 Flash illegal access event w rite invalid WPERR flag set Flash illegal access event Secure page SPC 1 2 Non secure page or secure page Bus error w rite invalid SECWPERR flag set Note 1 Booting from Flash and no debug access 2 Debug access is detected Table 2 6 Flash operation under different protection levels when TrustZone is disable TZEN 0 Access type Fetch Read...

Page 81: ...g set Flash illegal access event w rite invalid WPERR flag set Note 1 Bootingfrom Flashandno debug access 2 Debugaccess is detected 3 Others refer to other Flash security configurations that are different from the Flash security configuration described for DMP protection In QSPI mode when the user accesses the external Flash memory in violation of the Flash security attribute configured by secure ...

Page 82: ... is set in EFUSE first 32KB are write protect then a system reset is necessary When there are option bytes the write protected area defined in the option bytes FMC_OBR is also write protected Note This fuction is only available in FMC mode 2 4 11 Flash privileged and unprivileged mode The Flash registers can be read and written by privileged and unprivileged accesses depending on PRIV bit in FMC_P...

Page 83: ...secure Flag Description Clear method Interrupt enable bit SECENDF end of operation Write 1 to corresponding bit in FMC_SECSTAT register SECENDIE SECWPERR erase program on protected pages SECERRIE SECERR an invalid secure DMP area is defined DMPx_PEND SECMx_PEND ...

Page 84: ...s Fields Descriptions 31 0 KEY 31 0 FMC_CTL unlock register These bits are only be w ritten by softw are Write KEY 31 0 w ith keys to unlock FMC_CTL register 2 5 2 Option byte unlock key register FMC_OBKEY Address offset 0x08 Reset value 0x0000 0000 This register is non secure Protected against non provileged access when FMC_PRIV 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 ...

Page 85: ...oftw are can clear it by w riting 1 3 OBERR Option bytes error flag bit If there are option bytes If user set the TZEN bit w hen the Flash is not in no protection state this bit is set If user does not clear the TZEN bit at the same time w hen the Flash security protection returns to unprotected this bit is set If an invalid secure DMP area is defined DMPx_EPAGE SECMx_EPAGE this bit is set and the...

Page 86: ... only be w ritten if OBWEN bit is set This bit is only set by softw are and is cleared w hen the BUSY bit is cleared in FMC_STAT 13 Reserved Must be kept at reset value 12 ENDIE End of operation interrupt enable bit This bit is set or cleared by softw are 0 no interrupt generated by hardw are 1 end of operation interrupt enable 11 Reserved Must be kept at reset value 10 ERRIE Error interrupt enabl...

Page 87: ...mmand 0 PG Main Flash program command bit This bit is set or clear by softw are 0 no effect 1 main Flash program command Note This register should be reset after the corresponding Flash operation completed 2 5 5 Address register FMC_ADDR Address offset 0x14 Reset value 0x0000 0000 This register is non secure Protected against non provileged access when FMC_PRIV 1 This register has to be accessed b...

Page 88: ...e 5 FMCOB Whether the option byte exist or not 0 There are no option bytes 1 There are option bytes 4 NQSPI Memory structure is FMC mode or QSPI mode 0 QSPI mode EXT Flash 1 FMC mode SIP Flash 3 TZEN_STAT Trust zone state 0 Trust zone is disabled 1 Trust zone is enabled 2 WP Write erase protection state 0 w rite erase protection is reset 1 w rite erase protection is set 1 SPC Security protection l...

Page 89: ...ECSTAT Address offset 0x2C Reset value 0x0000 0000 This register is secure It can be read and written only by secure access A non secure read write access is RAZ WI This register can be protected against non privileged access when FMC_PRIV 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SECE...

Page 90: ...stalls till SECBSY and NSBSY are reset This register is secure It can be read and written only by secure access A non secure read write access is RAZ WI This register can be protected against non privileged access when FMC_PRIV 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SECENDI E Reserved...

Page 91: ... SECPER Main Flash page erase command bit This bit is set or clear by softw are 0 no effect 1 main Flash page erase command 0 SECPG Main Flash program command bit This bit is set or clear by softw are 0 no effect 1 main Flash program command Note This register should be reset after the corresponding Flash operation completed 2 5 10 Secure Address register FMC_SECADDR Address offset 0x34 Reset valu...

Page 92: ...rd 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TZEN Reserved SRAM1_ RST Reserved SPC 7 0 rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 TZEN Trust zone enable bit 0 Disable Trust zone function Effective after system reset 1 Enable Trust zone function Effective after system reset Note If there are option byte...

Page 93: ...te USER value Note If there are option bytes USER is subject to this bit field configuration otherw ise it is subject to the configuration in the EFUSE_USER_CTL register 2 5 13 Secure mark configuration register 0 FMC_SECMCFG0 Address offset 0x48 Reset value 0x03FF 0000 0xXXXX XXXX When there are option bytes register bits 0 to31 are loaded with values from Flash memory when OBRLD is set or system...

Page 94: ...is set This register is secure when TZEN 1 It can be read and written only by secure access or TZEN 0 A non secure read write access is RAZ WI This register can be protected against non privileged access when PRIV 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMP0EN Reserved DMP0_EPAGE 9 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits...

Page 95: ...t page of w rite protection area 0 2 5 16 Secure mark configuration register 1 FMC_SECMCFG1 Address offset 0x54 Reset value 0x0000 03FF 0xXXXX XXXX When there are option bytes register bits 0 to 31 are loaded with values from Flash memory when OBRLD is set or system reset When there no option bytes the reset value is kept at 0x0000 03FF This register can not be written if OBWEN bit is set This reg...

Page 96: ...otected against non privileged access when FMC_PRIV 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMP1EN Reserved DMP1_EPAGE 9 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits Fields Descriptions 31 DMP1EN DMP area 1 enable 0 disable 1 enable 30 26 Reserved Must be kept at reset value 25 16 DMP1_EPAGE 9 0 End page of DMP area 1 15 0 Re...

Page 97: ...FG2 Address offset 0x60 Reset value 0x0000 03FF This register can not be written if OBWEN bit is set This register is secure It can be read and written only by secure access A non secure read write access is RAZ WI This register can be protected against non privileged access when PRIV 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SECM2_E...

Page 98: ...6 SECM3_EPAGE 9 0 End page of secure mark area 3 15 10 Reserved Must be kept at reset value 9 0 SECM3_SPAGE 9 0 Start page of secure mark area 3 2 5 21 NO RTDEC region register x FMC_NODECx x 0 1 2 3 Address offset 0x70 0x4 x x 0 to 3 Reset value 0x0000 03FF This register can not be written if OBWEN bit is set This register is secure when TZEN 1 It can be read and written only by secure access or ...

Page 99: ...n privileged access when FMC_PRIV 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved OF_EPAGE 12 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OF_SPAGE 12 0 rw Bits Fields Descriptions 31 29 Reserved Must be kept at reset value 28 16 OF_EPAGE 12 0 End page of offset region 15 13 Reserved Must be kept at reset value 12 0 OF_SPAGE 12 0 St...

Page 100: ... access is RAZ WI This register can be protected against non privileged access when FMC_PRIV 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DMP1_A CCFG DMP0_A CCFG rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 DMP1_ACCFG DMP area 1 access configuration bit When se...

Page 101: ...0 FMC_PRIV This bit can be read by both privileged or unprivileged secure and non secure access When set it can only be cleared by a privileged access 0 All Flash registers can be read and w ritten by privileged or unprivileged access 1 All Flash registers can be read and w ritten by privileged access only If the Flash is not secure non secure area defined the FMC_PRIV bit can be w ritten by a sec...

Page 102: ...rs As a non volatile unit of storage the bit of efuse macro cannot be restored to 0 once it is programmed to 1 According tothesoftware operation theEFUSE controllercanprogram all bits inthesystemparameters 3 2 Characteristics One time programmable nonvolatile EFUSE storage cells organized as 256 8 bit All bits in the efuse cannot be rollback from 1 to 0 Can only be accessed through corresponding r...

Page 103: ...cells organized into 256 bytes EFUSE uses 8 bit address encoding The following table Table 3 1 EFUSE addressmapping shows the address Table 3 1 EFUSE addressmapping ADDR 7 0 EFUSE byte 0000_0000 EFUSE 0 0000_0001 EFUSE 1 0000_0010 EFUSE 2 1111_1111 EFUSE 255 3 4 2 EFUSE macro description The EFUSE macrostores18system parameters every system parameterhas different width The following table Table 3 ...

Page 104: ...n control register EFUSE_FP_CTL User define d User control 1B 8 d3 Can w rite multiple times but can not rollback Read out after system reset and keep unchanged bus readable The option of user control function For more details refer to User control register EFUSE_USER_CTL User define d MCU initialization parameters 12B 8 d4 once time Read only once after system reset bus readable The relevant para...

Page 105: ... d152 can not modify Read out after system reset and keep unchanged bus readable w hen rom_rd_en valid Hardw are Unique Key w hich provides the RoT Root of Trust for confidentiality For more details refer to HUK key register EFUSE_HUK_KEY CP RF data CCK Pow er Index 6Bx2 8 d168 Write once after system reset Read out after system reset bus readable w hen rom_rd_en valid CCK Tx pow er control index ...

Page 106: ...8 d 200 Write once after system reset Read out after system reset bus readable w hen rom_rd_en valid WLAN MAC address Custo mer trim 8 d 206 IC RF type 1Bx2 8 d 212 Write once after system reset Read out after system reset bus readable w hen rom_rd_en valid IC RF type related options Custo mer trim 8 d 213 Reserve d 1Bx2 8 d 214 Write once after system reset Read out after system reset bus readabl...

Page 107: ...Note When reading EFUSE block the whole block should be read back first and then the corresponding register content could be read 3 4 4 Program operation The value of the EFUSE can only be modified through the corresponding register The following steps show the register access sequence of the EFUSE writing operation 1 Clear the PGIF bit if it is SET and make sure there are no overstep boundary err...

Page 108: ...lear bit for overstep boundary error interrupt flag 0 No effect 1 Clear error flag 25 RDIC Clear bit for read operation completed interrupt flag 0 No effect 1 Clear read operation completed interrupt flag 24 PGIC Clear bit for program operation completed interrupt flag 0 No effect 1 Clear program operation completed interrupt flag 23 Reserved Must be kept at reset value 22 OVBERIE Enable bit for o...

Page 109: ...SA register contribute configuer 0 EFUSE_IAK_GSSA register for IAK 1 EFUSE_IAK_GSSA register for GSSA 14 2 Reserved Must be kept at reset value 1 EFRW The selection of efuse operation 0 Read EFUSE 1 Write EFUSE This bit cannot be modified w hen the EFSTR bit is 1 0 EFSTR Start EFUSE operation This bit is set by softw are and cleared by hardw are 0 No effect 1 Start read or w rite EFUSE operation 3...

Page 110: ...ved SWBOOT 0 EFBOOT 0 SWBOOT 1 EFBOOT 1 EFBOOT LK EFSB rw rw rw rw rw rw Bits Fields Descriptions 31 6 Reserved Must be kept at reset value 5 SWBOOT0 Efuse boot 0 bit enable 0 Select boot0_pad as BOOT0 output 1 Select efuse_boot0 as BOOT0 output 4 EFBOOT0 EFUSE boot0 0 Efuse_boot0 0 1 Efuse_boot0 1 3 SWBOOT1 EFUSE boot 1 bit enable 0 Select boot1_pad as BOOT1 output 1 Select efuse_boot1 as BOOT1 o...

Page 111: ...reset value 7 VFCERT Verify firmw are certificate 0 Disable firmw are certificate verification 1 Enable firmw are certificate verification 6 VFIMG Verify firmw are image 0 Disable firmw are image verification 1 Enable firmw are image verification 5 DPLK EFUSE_DP register lock bit 0 Unlock EFUSE_DP register 1 Lock EFUSE_DP register 4 IGLK EFUSE_IAK_GSSA register lock bit 0 Unlock EFUSE_IAK_GSSA reg...

Page 112: ...eserved FP 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 FP 7 0 Efuse flash protection value Bit 7 3 Reserved Bit2 0 32K w rite protection Bit1 Read protection level 0 5 Bit0 Read protection level 1 3 5 6 User control register EFUSE_USER_CTL Address offset 0x14 Reset value 0x0000 0006 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 2...

Page 113: ...TL register these bytes can be modified w hen parameters have never been w ritten 1 Lock EFUSE_FP_CTL and EFUSE_USER_CTL register these bytes can not be modified 2 NRSTDPSLP Reset option of entry deep sleep mode 0 Generate a reset instead of entering Deep sleep mode 1 No reset w hen entering Deep sleep mode 1 NRSTSTDBY Reset option of entry standby mode 0 Generate a reset instead of entering stand...

Page 114: ... Descriptions 31 0 AESKEY 31 0 EFUSE AES key value 3 5 9 RoTPK key register EFUSE_ROTPK_KEY Address offset 0x34 X 4 X 0 1 2 3 7 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RKEY 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RKEY 15 0 rw Bits Fields Descriptions 31 0 RKEY 31 0 EFUSE RoTPK or its hash value 3 5 10 Debug pass...

Page 115: ...0 19 18 17 16 IAKGSSA 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IAKGSSA 15 0 rw Bits Fields Descriptions 31 0 IAKGSSA 31 0 EFUSE IAK GSSA value The properties of this register depend on the IAKSEL bit in the EFUSE_CS register 3 5 12 Product UID register EFUSE_PUID Address offset 0x9C X 4 X 0 1 2 3 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 ...

Page 116: ...er EFUSE_RF_DATA Address offset 0xBC X 4 X 0 1 2 3 11 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RFDATA 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFDATA 15 0 rw Bits Fields Descriptions 31 0 RFDATA 31 0 EFUSE RF data value 3 5 15 User data register EFUSE_USER_DATA Address offset 0xEC X 4 X 0 1 2 3 7 Reset value 0x000...

Page 117: ...tions 31 1 Reserved Must be kept at reset value 0 STZEN Enable Trustzone function by softw are This bit w ill not be w ritten to the efuse thus it can rollback to 0 0 Disable trust zone function 1 Enable trust zone function 3 5 17 TrustZone boot address register EFUSE_TZ_BOOT_ADDR Address offset 0x120 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 2...

Page 118: ...t 0x124 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NTZBOOTADDR 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NTZBOOTADDR 15 0 r Bits Fields Descriptions 31 0 NTZBOOTADDR 31 0 Boot from the address w hen TrustZone is disabled ...

Page 119: ...st bus while master 1 port outputs to slow bus Cache access support hit under miss and paired master access feature Support memory address remap Support pLRU replacement policy and critical word first refill policy Support remap region AHB transaction burst type configuration Support two performance counters 32 bit hit monitor counter and16 bit miss monitor counter Operation management Cache inval...

Page 120: ...e operation is ended all cache line valid bit will be cleared and BUSY flag is reset while END flag is set To ensure performance it is necessary to check if cache invalidate operation completed before enabling the ICACHE Application necessarily check BUSY and END flag in ICACHE_STAT before enabling the ICACHE In case that ICACHE is enabled before invalidate operation ended during this period on th...

Page 121: ...cache line index inside a way furthermore check if the requested data is valid in cache ICACHE main parameters of TAG memory for default 2 way set associative is shown in Table 4 1 TAG memory parameters Table 4 1 TAG memory parameters Parameter Value Cache size 32KB Cache w ays number 2 Cache line size 128 bit Cache lines number 1024 per w ay Address byte offset size 4 bit Address w ay index size ...

Page 122: ...gured by programming ICACHE_CFGx register the programming operation is merely done in case that ICACHE is disabled While once the EN bit in ICACHE_CFGx register is set even though ICAHCE is disabled or the transaction is uncacheable the corresponding region x is enabled and then remap operation is generated The SIZE bit in ICACHE_CFGx register is used to configure remap region size The size of reg...

Page 123: ...d remap address firstly and then cached The target physical address does not need further operation The remapping functionality is remain available even if cache is disabled and traffic is uncacheable If there is a memory uncacheable access ICACHE is ignored so that the AHB transaction is transmitted directly unchanged to the master output port while depending on remapping feature only transaction...

Page 124: ...from main memory processor get lower power consumption in fetching instructions from internal ICACHE If the cached memory is external power saving is more obvious 4 3 6 ICACHE performance monitoring For analyzing cache performance ICACHE support two monitors a 32 bit hit monitor and a 16 bit miss monitor they are disabled by default Hit monitor counts the AHB transactions on ICACHE input port whic...

Page 125: ...nding interrupt enable bit is set end interrupt is triggered and then cache is available again Table 4 5 ICACHE interrupt ICACHE error end Interrupt event Functional error Operation end Event flag ERR END Interrupt enable bit ERRIE ENDIE Interrupt clear bit ERRC ENDC ...

Page 126: ... reset 0 no effect 1 reset cache miss monitor 18 HMRST Hit monitor reset 0 no effect 1 reset cache hit monitor 17 MMEN Miss monitor enable 0 sw itch off cache miss monitor stopping the monitor and does not reset 1 cache miss monitor enabled 16 HMEN Hit monitor enable 0 sw itch off cache hit monitor stopping the monitor and does not reset 1 cache hit monitor enabled 15 4 Reserved Must be kept at re...

Page 127: ...ons 31 3 Reserved Must be kept at reset value 2 ERR Cache error flag 0 no error 1 error occurred during the operation 1 END operation end flag 0 cache busy 1 invalidate INVAL operation ended 0 BUSY Busy flag 0 cache is not executing a invalidate operation 1 cache is executing a invalidate operation 4 4 3 Interrupt enable register ICACHE_INTEN Address offset 0x08 Reset value 0x0000 0000 This regist...

Page 128: ...o be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ERRC ENDC Reserved w w Bits Fields Descriptions 31 3 Reserved Must be kept at reset value 2 ERRC Softw are clear cache error flag 0 no effect 1 clears ERR flag in ICACHE_STAT 1 ENDC Softw are clear operation end flag 0 no effect 1 clears END flag in ICACHE_STAT 0 Res...

Page 129: ...4 3 2 1 0 MMC 15 0 r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 MMC 15 0 Cache miss monitor counter 4 4 7 Configuration register ICACHE_CFGx Address offset 0x20 4 x x 0 3 Reset value 0x0000 0200 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OBT Reserved MSEL Reserved RADDR rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 130: ...on x remapped address this field replaces the alias address defined by BADDR field 15 EN Region x enable 0 disabled 1 enabled 14 12 Reserved Must be kept at reset value 11 9 SIZE Region x size 000 reserved 001 2 Mbytes 010 4 Mbytes 011 8 Mbytes 100 16 Mbytes 101 32 Mbytes 110 64 Mbytes 111 128 Mbytes 8 Reserved Must be kept at reset value 7 0 BADDR Region x base address ...

Page 131: ...bedded LDO in the VDD VDDA domain is usedtosupply the1 2V domainpower Apowerswitch isimplementedfortheBackupdomain It can be powered from the VBAT voltage when the main VDD supply is shut down 5 2 Characteristics Three power domains VBAK VDD VDDA and 1 2V power domains Five power saving modes Sleep Deep sleep Standby SRAM_sleep and Wi Fi_sleep modes Internal Voltage regulator LDO supplies around 1...

Page 132: ...the VBAK pin which drives Backup Domain power supply for RTC unit LXTAL oscillator BPOR and two pads including PC14 to PC15 In order to ensure the content of the Backup domain registers and the RTC supply when VDD supply is shut down VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source The power switch is controlled by the Power Down Reset circuit in ...

Page 133: ... only be obtained by a small current the speed of GPIOs PC14 to PC15 should not exceed 2MHz when they are in output mode maximum load 30pF 5 3 2 VDD VDDA power domain VDD VDDA domain includes two parts VDD domain and VDDA domain VDD domain includes HXTAL High Speed Crystal oscillator LDO Voltage Regulator POR PDR Power On Down Reset FWDGT Free Watchdog Timer all pads except PC14 PC15 etc VDDA doma...

Page 134: ...ld This event is internally connected to the EXTI line 16 and can generate an interrupt if it is enabled through the EXTI registers Figure 4 5 Waveform of the LVD threshold shows the relationship between the LVD threshold and the LVDoutput LVD interrupt signal depends onEXTI line16 risingor falling edgeconfiguration The following figure shows the relationship between the supply voltage and the LVD...

Page 135: ...omainandthe VDD VDDA domain etc arelocatedinthis powerdomain Once the 1 2V is powered up the POR will generate a reset sequence on the 1 2V power domain If need to enter the expected power saving mode the associated control bits must be configured Then once a WFI Wait for Interrupt or WFE Wait for Event instruction is executed the device will enter an expected power saving mode which will be discu...

Page 136: ...33 System Control Register there are two options to select the Sleep mode entry mechanism Sleep now if the SLEEPONEXIT bit is cleared the MCU enters Sleep mode as soon as WFI or WFE instruction is executed Sleep on exit if the SLEEPONEXIT bit is set the MCU enters Sleep mode as soon as it exits from the lowest priority ISR Deep sleep mode The Deep sleepmodeis basedonthe SLEEPDEEPmodeoftheCortex M3...

Page 137: ...be reset If not the program will skip the entry process of Deep sleep mode to continue to execute the following procedure Standby mode The Standby mode is based on the SLEEPDEEP mode of the Cortex M33 too In Standby mode the whole 1 2V domain is power off the LDO is shut down and all of IRC16M HXT AL and PLLs are disabled Before entering the Standby mode it is necessary to set the SLEEPDEEP bit in...

Page 138: ...e Wi Fi_OFF domain power off When exit from Wi Fi_sleep mode Wi Fi is active mode all Wi Fi power domain power on Table 4 6 Typical work mode Power mode MCU Wi Fi Consumption Discription Wi Fi tx Run TX 451mA All w ork Wi Fi rx Run RX 127mA All w ork Modem sleep Run Disable 30 69mA Wi Fi_OFF pow er off RF pow er off Sensor hub Sleep SRAM_sleep Disable 100 800uA MCU sleep CORE_MEM1 2 3 pow er off W...

Page 139: ...o Table 4 7 Time in RF sequence value in order of Figure 4 6 RF sequence When set WPWAKE bit to 1 or Wi Fi hardware signal wake_wl is valid RFPLL XT AL BG RF ANA clocks will be automatically opened according to Table 4 7 Time in RF sequence value in order of Figure 4 6 RF sequence If RFSWEN bit is 1 choose software mode to configure RF sequence RFPLL XTAL BG RFANA clocks will be openedor closed by...

Page 140: ...ff LDO Status On On or in low pow er mode or low driver mode Off On or in low pow er mode or low driver mode On or in low pow er mode or low driver mode Configurat ion SLEEPDEE P 0 SLEEPDEEP 1 STBMOD 0 SLEEPDEEP 1 STBMOD 1 WURST 1 SRAMxPSLEE P 1 x 1 2 3 1 WPEN 1 WPSLEEP 1 2 Or hardw are signal sleep_w l valid w hen WPEN 1 Entry WFI or WFE WFI or WFE WFI or WFE Wakeup Any interrupt for WFI Any even...

Page 141: ...ster is set PRIV bit in PMU_PRICFG register Read is OK WI and illegal access event 2 LPMSEC in PMU_SECCFG register is set LDOLP STBMOD WURST and STBRST bits in PMU_CTL0 register RAZ WI LPMSEC or WUPxSEC in PMU_SECCFG register is set WUPENx bits in PMU_CS0 register RAZ WI VDMSEC in PMU_SECCFG register is set LVDEN LVDT 2 0 and VLVDEN bits in PMU_CTL0 register RAZ WI DBPSEC in PMU_SECCFG register is...

Page 142: ...upported or not When PRIV bit is reset both privileged and unprivileged accesses to PMU registers are supported When PRIV bit is set only privileged access to PMU registers is supported unprivileged access to a privileged register is RAZ WI ...

Page 143: ...URST STBMOD LDOLP rs rw rw rw rw rw rw rc_w1 rc_w1 rw rw Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 18 LDEN 1 0 Low driver mode enable in Deep sleep mode 00 Low driver mode disable in Deep sleep mode 01 Reserved 10 Reserved 11 Low driver mode enable in Deep sleep mode 17 16 Reserved Must be kept at reset value 15 14 LDOVS 1 0 LDO output voltage select These bits are set...

Page 144: ...e access to these registers 7 5 LVDT 2 0 Low Voltage Detector Threshold 000 2 1V 001 2 3V 010 2 4V 011 2 6V 100 2 7V 101 2 9V 110 3 0V 111 3 1V 4 LVDEN Low Voltage Detector Enable 0 Disable Low Voltage Detector 1 Enable Low Voltage Detector 3 STBRST Standby Flag Reset 0 No effect 1 Reset the standby flag This bit is alw ays read as 0 2 WURST Wakeup Flag Reset 0 No effect 1 Reset the w akeup flag T...

Page 145: ... Deep sleep mode and the LDO in Low driver mode These bits are cleared by softw are w hen w rite 11 00 normal driver in Deep sleep mode 01 Reserved 10 Reserved 11 Low driver mode in Deep sleep mode 17 15 Reserved Must be kept at reset value 14 LDOVSRF LDO voltage select ready flag 0 LDO voltage select not ready 1 LDO voltage select ready 13 12 Reserved Must be kept at reset value 11 WUPEN3 WKUP Pi...

Page 146: ...mode As the WKUP pin0 is active high the WKUP pin0 is internally configured to input pull dow n mode And set this bit w ill trigger a w akup event w hen the input is aready high 7 4 Reserved Must be kept at reset value 3 VLVDF VDDA Low Voltage Detector Status Flag 0 Low Voltage event has not occurred VDDA is higher than the specified threshold 2 4V 1 Low Voltage event occurred VDDA is equal to or ...

Page 147: ...Reserved Must be kept at reset value 10 SRAM2PWAKE SRAM2 w akeup by softw are Clear by hardw are 9 SRAM2PSLEEP SRAM2 go to sleep by softw are Clear by hardw are 8 7 Reserved Must be kept at reset value 6 SRAM1PWAKE SRAM1 w akeup by softw are Clear by hardw are 5 SRAM1PSLEEP SRAM1 go to sleep by softw are Clear by hardw are 4 Reserved Must be kept at reset value 3 WPWAKE Wi Fi w akeup Only w hen WP...

Page 148: ...AM1PS _ACTIVE SRAM1PS _SLEEP Reserved WPS_ACT IVE WPS_SLE EP Reserved r r r r r r r r Bits Fields Descriptions 31 15 Reserved Must be kept at reset value 14 SRAM3PS_ACTIVE SRAM3 is in active state Read only 13 SRAM3PS_SLEEP SRAM3 is in sleep state Read only 12 11 Reserved Must be kept at reset value 10 SRAM2PS_ACTIVE SRAM2 is in active state Read only 9 SRAM2PS_SLEEP SRAM2 is in sleep state Read o...

Page 149: ...uence opening process 0 RFSWEN 1 RF sequence configured by softw are 0 RF sequence configured automatically by hardw are according to Figure 4 6 RF sequence default 5 4 6 Secure configuration register PMU_SECCFG Address offset 0x30 Reset value 0x0000 0000 not reset by wakeup from Standby mode A non secure write access is WI and generates an illegal access event There are no read restrictions When ...

Page 150: ...bits is RAZ WI 7 4 Reserved Must be kept at reset value 3 WUP3SEC WKUP pin 3 security When set WUPEN3 bit in PMU_CS0 register is secure A non secure read w rite access on secured bits is RAZ WI 2 WUP2SEC WKUP pin 2 security When set WUPEN2 bit in PMU_CS0 register is secure A non secure read w rite access on secured bits is RAZ WI 1 WUP1SEC WKUP pin 1 security When set WUPEN1 bit in PMU_CS0 registe...

Page 151: ...MU registers can be read and w ritten w ith privileged or unprivileged access 1 All PMU registers can be read and w ritten only w ith privileged access An unprivileged access to PMU registers is RAZ WI If the PMU is not secure the PRIV bit can be w ritten by a secure or non secure privileged access If TrustZone security is enabled TZEN 1 if the PMU is secure the PRIV bit can be w ritten only by a ...

Page 152: ...generator when exiting Standby mode The power reset sets all registers to their reset values except the Backup domain The Power reset whose active signal is low it will be de asserted when the internal LDO voltage regulator is ready to provide 1 2V power System reset A system reset is generated by the following events A power reset POWER_RSTn A external pin reset NRST A window watchdog timer reset...

Page 153: ...clock functions These include a Internal 16M RC oscillator IRC16M a High Speed crystal oscillator HXTAL a Low Speed Internal 32K RC oscillator IRC32K a Low Speed crystal oscillator LXTAL three Phase Lock Loop PLL PLLDIG PLLI2S two HXTAL clock monitor clock prescalers clock multiplexers and clock gatingcircuitry The clocks of the AHB APB and Cortex M33are derived from the system clock CK_SYS whichc...

Page 154: ...CKOUT0DIV 1 2 3 4 5 xN VCO PLL 180 MHz max 180 MHz max 00 01 10 CK_HPDFAU DIO to HPDFAUDIO Peripheral enable CK_OUT1 CK_PLLDIG CK_HXTAL CK_SYS CK_PLLI2S 11 00 01 10 CKOUT1SEL 1 0 CKOUT1DIV 1 2 3 4 5 CK_HXTAL to USBFS TRNG Peripheral enable 0 1 USBFSSEL PSC 0 1 PLLSEL IRC16 MDIV 11 PLLP DIGFS YSDIV CK_PLLDIG USBFSDIV to SDIO Peripheral enable SDIOSEL SDIODIV xN VCO PLLDIG xN VCO PLLI2S PLLI2SDIV PL...

Page 155: ...he RTC is clocked by LXTAL clock or IRC32K clock or HXTAL clock divided by 2 to 32 defined by RTCDIV bits in RCU_CFG0 which select by RTCSRC bit in Backup Domain Control Register RCU_BDCTL After the RTC select HXTAL clock divided by 2 to 31 defined by RTCDIV bits in RCU_CFG0 the clock disappeared when the 1 2V core domain power off After the RTC select IRC32K the clock disappeared when VDD power o...

Page 156: ...red up it will not be released for use until this HXTALSTB bit is set by the hardware This specific delay period is known as the oscillator Start up time As the HXTAL becomes stable an interrupt will be generated if the related inte rrupt enable bit HXTALSTBIE in the Interrupt Register RCU_INT is set At this point t he HXTAL clock can be used directly as the system clock source or the PLL input cl...

Page 157: ...e PLLEN bit in the RCU_CTL Register The PLLSTB flag in the RCU_CTL Register will indicate if the PLL clock is stable An interrupt can be generated if the related interrupt enable bit PLLSTBIE in the RCU_INT Register is set as the PLL becomes stable The PLLI2S can be switched on or off by using the PLLI2SEN bit in the RCU_CTL Register The PLLI2SSTB flag in the RCU_CTL Register will indicate if the ...

Page 158: ...is changed the CK_SYS will continue to operate using the original clock source until the target clock source is stable When a clock source is directly or indirectly by PLL or PLLDIG used as the CK_SYS it is not possible to stop it HXTAL clock monitor CKM The HXTAL clock monitor function is enabled by the HXTAL Clock Monitor Enable bit CKMEN in the Control Register RCU_CTL This function should be e...

Page 159: ...ster RCU_CFG0 Voltage control The 1 2V domain voltage in Deep sleep mode can be controlled by DSLPVS 2 0 bit in the Deep sleep mode voltage register RCU_DSV 1 2V domain voltage selectedin deep sleep mode Table 6 3 1 2V domain voltage selected in deep sleep mode DSLPVS 1 0 Deep sleep mode voltage V 00 1 1 01 1 0 10 0 9 11 0 8 The RCU_DSV register are protected by Voltage Key register RCU_VKEY Only ...

Page 160: ...ecure protection configuration summary Configuration bit in RCU_SECPCFG Corresponding register Secured bit IRC16MSECP 1 RCU_CTL IRC16MEN IRC16MSTB IRC16MADJ IRC16MCALIB RCU_INT IRC16MSTBIE IRC16MSTBIF IRC16MSTBIC IRC16MSTBIF RCU_CFG1 IRC16MDIV HXTALSECP 1 RCU_CTL HXTALEN HXTALSTV HXTALBPS CKMEN RFCKME N HXTALPU HXTALENI2S HSTALENPLL HATALREA DY RCU_INT CKMIC HXTALSTBIC HXTALSTBIE CKMIF HXTALSTBIF ...

Page 161: ...ure access Secure bit allow ed RAZ no illegal access event allow ed WI no illegal access event Nonsecure bit allow ed allow ed allow ed allow ed RCU_SECP_CFG allow ed RAZ generates an illegal access event 1 allow ed WI generates an illegal access event 1 NOTE 1 An illegal access interrupt is generated if the RCU illegal access interrupt is enabled in the TZIAC_INTEN2 register 6 4 RCU privilege pro...

Page 162: ...GD32W51x User Manual 162 Access mode Read Write Priviledg access Unprivileg access Priviledg access Unprivileg access SECP_STAT RCUP RIP in RCU_CTL ...

Page 163: ... can not be w ritten w hen HXTALEN HXTALENI2S HXTALENPLL or PLLDIGEN is enable 0 HXTAL is not ready set by softw are 1 HXTAL is ready set by softw are 30 HXTALENPLL High Speed crystal oscillator enable for system CK_PLLP w hich can be w ritten w hen PLL is off Set and reset by softw are Reset by hardw are w hen entering Deep sleep or Standby mode 0 High speed crystaloscillator for CK_PLLP disable ...

Page 164: ...as the system clock Reset by hardw are w hen entering Deep sleep or Standby mode 0 PLL disable 1 PLL enbale 23 PLLDIGSTB PLLDIG Clock Stabilization Flag Set by hardw are to indicate if the PLLDIG output clock is stable and ready for use 0 PLLDIG is not stable 1 PLLDIG is stable 22 RFCKMEN HXTAL Clock Monitor Enable Check RF XTAL 0 Disable the High speed crystal oscillator HXTAL clock monitor 1 Ena...

Page 165: ...XTAL enable Set and reset by softw are This bit cannot be reset if the HXTAL clock is used as the system clock or the PLL input clock w hen PLL clock is selected to the system clock Reset by hardw are w hen entering Standby mode If enable PLLDIG or RFPLL this bit need be set to 1 0 High speed crystaloscillator disabled 1 High speed crystaloscillator enabled 15 8 IRC16MCALIB 7 0 Internal 16MHz RC O...

Page 166: ...er RCU_PLL Address offset 0x04 Reset value 0x0000 3010 To configure the PLL clock refer to the following formula CK_PLLVCOSRC CK_PLLSRC PLLPSC CK_PLLVCO CK_PLLVCOSRC PLLN CK_PLLP CK_PLLVCO PLLP This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PLLP 1 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PLLSEL PLLN 8 0 PLLPSC...

Page 167: ..._PLLSSCTL 75 PLLN 508 w hen SSCGON 1 SS_TYPE 1 in RCU_PLLSSCTL 000000000 Reserved 000000001 Reserved 000111111 Reserved 001000000 CK_PLLVCO CK_PLLVCOSRC x 64 001000001 CK_PLLVCO CK_PLLVCOSRC x 65 111111110 CK_PLLVCO CK_PLLVCOSRC x 510 111111111 CK_PLLVCO CK_PLLVCOSRC x 511 5 0 PLLPSC 5 0 The PLL VCO source clock prescaler Set and reset by softw are w hen the PLL is disable These bits used to gener...

Page 168: ...0 The CK_OUT1 is divided by 4 111 The CK_OUT1 is divided by 5 26 24 CKOUT0DIV 2 0 The CK_OUT0 divider w hich the CK_OUT0 frequency can be reduced see bits 22 21 of RCU_CFG0 for CK_OUT0 0xx The CK_OUT0 is divided by 1 100 The CK_OUT0 is divided by 2 101 The CK_OUT0 is divided by 3 110 The CK_OUT0 is divided by 4 111 The CK_OUT0 is divided by 5 23 Reserved Must be kept at reset value 22 21 CKOUT0SEL...

Page 169: ...010 CK_SYS 8 selected 1011 CK_SYS 16 selected 1100 CK_SYS 64 selected 1101 CK_SYS 128 selected 1110 CK_SYS 256 selected 1111 CK_SYS 512 selected 3 2 SCSS 1 0 System clock sw itch status Set and reset by hardw are to indicate the clock source of system clock 00 select CK_IRC16M as the CK_SYS source 01 select CK_HXTAL as the CK_SYS source 10 select CK_PLLP as the CK_SYS source 11 select CK_PLLDIG as...

Page 170: ... IRC16MS TBIF LXTALST BIF IRC32KS TBIF rw rw rw rw rw rw rw r r r r r r r r Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 CKMIC HXTAL clock stuck interrupt clear Write 1 by softw are to reset the CKMIF flag 0 Not reset CKMIF flag 1 Reset CKMIF flag 22 PLLDIGSTBIC PLLDIG stabilization interrupt clear Write 1 by softw are to reset the PLLDIGSTBIF flag 0 Not reset PLLDIGSTBIF...

Page 171: ...errupt enable Set and reset by softw are to enable disable the PLLI2S stabilization interrupt 0 Disable the PLLI2S stabilization interrupt 1 Enable the PLLI2S stabilization interrupt 12 PLLSTBIE PLL Stabilization interrupt enable Set and reset by softw are to enable disable the PLL stabilization interrupt 0 Disable the PLL stabilization interrupt 1 Enable the PLL stabilization interrupt 11 HXTALST...

Page 172: ...1 PLLI2S stabilization interrupt generated 4 PLLSTBIF PLL stabilization interrupt flag Set by hardw are w hen the PLL is stable and the PLLSTBIE bit is set Reset w hen setting the PLLSTBIC bit by softw are 0 No PLL stabilization interrupt generated 1 PLL stabilization interrupt generated 3 HXTALSTBIF HXTAL stabilization interrupt flag Set by hardw are w hen the High speed 20 52 MHz crystaloscillat...

Page 173: ...cessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved USBFSR ST Reserved DMA1RS T DMA0RS T Reserved rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WIFIRST CRCRST Reserved TSIRST TZGPCR ST Reserved PCRST PBRST PARST rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 USBFSRST USBFS reset This b...

Page 174: ...are 0 No reset 1 Reset the TZGPC 6 3 Reserved Must be kept at reset value 2 PCRST GPIO port C reset This bit is set and reset by softw are 0 No reset 1 Reset the GPIO port C 1 PBRST GPIO port B reset This bit is set and reset by softw are 0 No reset 1 Reset the GPIO port B 0 PARST GPIO port A reset This bit is set and reset by softw are 0 No reset 1 Reset the GPIO port A 6 5 6 AHB2 reset register ...

Page 175: ...et the HAU 4 CAURST CAU reset This bit is set and reset by softw are 0 No reset 1 Reset the CAU 3 PKCAURST PKCAU reset This bit is set and reset by softw are 0 No reset 1 Reset the PKCAU 2 1 Reserved Must be kept at reset value 0 DCIRST DCI reset This bit is set and reset by softw are 0 No reset 1 Reset the DCI 6 5 7 AHB3 reset register RCU_AHB3RST Address offset 0x18 Reset value 0x0000 0000 This ...

Page 176: ...it half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PMURST Reserved I2C1RST I2C0RST Reserved USART0 RST USART1 RST Reserved rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SPI1RST Reserved WWDGT RST Reserved TIMER5R ST TIMER4R ST TIMER3R ST TIMER2R ST TIMER1R ST rw rw rw rw rw rw rw Bits Fields Descriptions 31 29 Reserved Must be kept at reset...

Page 177: ... SPI1 reset This bit is set and reset by softw are 0 No reset 1 Reset the SPI1 13 12 Reserved Must be kept at reset value 11 WWDGTRST WWDGT reset This bit is set and reset by softw are 0 No reset 1 Reset the WWDGT 10 5 Reserved Must be kept at reset value 4 TIMER5RST TIMER5 reset This bit is set and reset by softw are 0 No reset 1 Reset the TIMER5 3 TIMER4RST TIMER4 reset This bit is set and reset...

Page 178: ...ved rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SYSCFG RST Reserved SPI0RST SDIORST Reserved ADC0RS T Reserved USART2 RST Reserved TIMER0R ST rw rw rw rw rw rw Bits Fields Descriptions 31 RFRST RF reset This bit is set and reset by softw are 0 No reset 1 Reset the RF 30 HPDFRST HPDF reset This bit is set and reset by softw are 0 No reset 1 Reset the HPDF 29 19 Reserved Must be kept ...

Page 179: ...d Must be kept at reset value 8 ADC0RST ADC0 reset This bit is set and reset by softw are 0 No reset 1 Reset the ADC0 7 5 Reserved Must be kept at reset value 4 USART2RST USART2 reset This bit is set and reset by softw are 0 No reset 1 Reset the USART2 3 1 Reserved Must be kept at reset value 0 TIMER0RST TIMER0 reset This bit is set and reset by softw are 0 No reset 1 Reset the TIMER0 6 5 10 AHB1 ...

Page 180: ...lue 22 DMA1EN DMA1 clock enable This bit is set and reset by softw are 0 Disabled DMA1 clock 1 Enabled DMA1 clock 21 DMA0EN DMA0 clock enable This bit is set and reset by softw are 0 Disabled DMA0 clock 1 Enabled DMA0 clock 20 Reserved Must be kept at reset value 19 SRAM3EN SRAM3 clock enable This bit is set and reset by softw are 0 Disabled SRAM3 clock 1 Enabled SRAM3 clock 18 SRAM2EN SRAM2 clock...

Page 181: ...9 Reserved Must be kept at reset value 8 TSIEN TSI clock enable This bit is set and reset by softw are 0 Disabled TSI clock 1 Enabled TSI clock 7 TZGPCEN TZGPC clock enable This bit is set and reset by softw are 0 Disabled TZGPC clock 1 Enabled TZGPC clock 6 3 Reserved Must be kept at reset value 2 PCEN GPIO port C clock enable This bit is set and reset by softw are 0 Disabled GPIO port C clock 1 ...

Page 182: ...ept at reset value 6 TRNGEN TRNG clock enable This bit is set and reset by softw are 0 Disabled TRNG clock 1 Enabled TRNG clock 5 HAUEN HAU clock enable This bit is set and reset by softw are 0 Disabled HAU clock 1 Enabled HAU clock 4 CAUEN CAU clock enable This bit is set and reset by softw are 0 Disabled CAU clock 1 Enabled CAU clock 3 PKCAUEN PKCAU clock enable This bit is set and reset by soft...

Page 183: ...abled QSPI clock 0 SQPIEN SQPI clock enable This bit is set and reset by softw are 0 Disabled SQPI clock 1 Enabled SQPI clock 6 5 13 APB1 enable register RCU_APB1EN Address offset 0x40 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PMUEN Reserved I2C1EN I2C0EN Reserved USART0 EN USART1 EN...

Page 184: ...softw are 0 Disabled USART0 clock 1 Enabled USART0 clock 17 USART1EN USART1 clock enable This bit is set and reset by softw are 0 Disabled USART1 clock 1 Enabled USART1 clock 16 15 Reserved Must be kept at reset value 14 SPI1EN SPI1 clock enable This bit is set and reset by softw are 0 Disabled SPI1 clock 1 Enabled SPI1 clock 13 12 Reserved Must be kept at reset value 11 WWDGTEN WWDGT clock enable...

Page 185: ...k 6 5 14 APB2 enable register RCU_APB2EN Address offset 0x44 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RFEN HPDFEN Reserved TIMER16 EN TIMER15 EN Reserved rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SYSCFG EN Reserved SPI0EN SDIOEN Reserved ADC0EN Reserved USART2 EN Reserved TI...

Page 186: ...st be kept at reset value 12 SPI0EN SPI0 clock enable This bit is set and reset by softw are 0 Disabled SPI0 clock 1 Enabled SPI0 clock 11 SDIOEN SDIO clock enable This bit is set and reset by softw are 0 Disabled SDIO clock 1 Enabled SDIO clock 10 9 Reserved Must be kept at reset value 8 ADC0EN ADC0 clock enable This bit is set and reset by softw are 0 Disabled ADC0 clock 1 Enabled ADC0 clock 7 5...

Page 187: ...ck enable w hen sleep mode This bit is set and reset by softw are 0 Disabled USBFS clock w hen sleep mode 1 Enabled USBFS clock w hen sleep mode 28 23 Reserved Must be kept at reset value 22 DMA1SPEN DMA1 clock enable w hen sleep mode This bit is set and reset by softw are 0 Disabled DMA1 clock w hen sleep mode 1 Enabled DMA1 clock w hen sleep mode 21 DMA0SPEN DMA0 clock enable w hen sleep mode Th...

Page 188: ...d WIFIRUN clock w hen sleep mode 13 WIFISPEN Wi Fi clock enable w hen sleep mode This bit is set and reset by softw are 0 Disabled Wi Fi clock w hen sleep mode 1 Enabled Wi Fi clock w hen sleep mode 12 CRCSPEN CRC clock enable w hen sleep mode This bit is set and reset by softw are 0 Disabled CRC clock w hen sleep mode 1 Enabled CRC clock w hen sleep mode 11 9 Reserved Must be kept at reset value ...

Page 189: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRNGSP EN HAUSPE N CAUSPE N PKCAUS PEN Reserved DCISPEN rw rw rw rw rw Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 TRNGSPEN TRNG clock enable w hen sleep mode This bit is set and reset by softw are 0 Disabled TRNG clock w hen sleep mode 1 Enabled TRNG clock w hen sleep m...

Page 190: ... 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved QSPISPE N SQPISPE N rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 QSPISPEN QSPI clock enable w hen sleep mode This bit is set and reset by softw are 0 Disabled QSPI clock w hen sleep mode 1 Enabled QSPI clock w hen sleep mode 0 SQPISPEN SQPI clock enable w hen sleep mode This bit is set and reset b...

Page 191: ... I2C1 clock w hen sleep mode 1 Enabled I2C1 clock w hen sleep mode 21 I2C0SPEN I2C0 clock enable w hen sleep mode This bit is set and reset by softw are 0 Disabled I2C0 clock w hen sleep mode 1 Enabled I2C0 clock w hen sleep mode 20 19 Reserved Must be kept at reset value 18 USART0SPEN USART0 clock enable w hen sleep mode This bit is set and reset by softw are 0 Disabled USART0 clock w hen sleep m...

Page 192: ...d TIMER3 clock w hen sleep mode 1 Enabled TIMER3 clock w hen sleep mode 1 TIMER2SPEN TIMER2 clock enable w hen sleep mode This bit is set and reset by softw are 0 Disabled TIMER2 clock w hen sleep mode 1 Enabled TIMER2 clock w hen sleep mode 0 TIMER1SPEN TIMER1 clock enable w hen sleep mode This bit is set and reset by softw are 0 Disabled TIMER1 clock w hen sleep mode 1 Enabled TIMER1 clock w hen...

Page 193: ...w are 0 Disabled TIMER15 clock w hen sleep mode 1 Enabled TIMER15 clock w hen sleep mode 16 15 Reserved Must be kept at reset value 14 SYSCFGSPEN SYSCFG clock enable w hen sleep mode This bit is set and reset by softw are 0 Disabled SYSCFG clock w hen sleep mode 1 Enabled SYSCFG clock w hen sleep mode 13 Reserved Must be kept at reset value 12 SPI0SPEN SPI0 clock enable w hen sleep mode This bit i...

Page 194: ...by byte 8 bit half word 16 bit and word 32 bit Note The LXTALEN LXTALBPS RTCSRC and RTCEN bits of the Backup domain control register RCU_BDCTL are only reset after a Backup domain Reset These bits can be modified only when the BKPWEN bit in the Power control register PMU_CTL is set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved BKPRST rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCEN Reserv...

Page 195: ...ty 11 highest driving capability reset value Note The LXTALDRI is not in bypass mode 2 LXTALBPS LXTAL bypass mode enable Set and reset by softw are 0 Disable the LXTAL Bypass mode 1 Enable the LXTAL Bypass mode 1 LXTALSTB Low speed crystaloscillator stabilization flag Set by hardw are to indicate if the LXTAL output clock is stable and ready for use 0 LXTAL is not stable 1 LXTAL is stable 0 LXTALE...

Page 196: ...mer reset generated Reset by w riting 1 to the RSTFC bit 0 No free w atchdog timer reset generated 1 free Watchdog timer reset generated 28 SWRSTF Softw are reset flag Set by hardw are w hen a softw are reset generated Reset by w riting 1 to the RSTFC bit 0 No softw are reset generated 1 Softw are reset generated 27 PORRSTF Pow er reset flag Set by hardw are w hen a Pow er reset generated Reset by...

Page 197: ...pectrum modulation is available only for the main PLL clock The RCU_PLLSSCTL register must be written when the main PLL is disabled This register is used to configure the PLL spread spectrum clock generation according to the following formulas MODCNT round fPLLIN 4 fmod MODSTEP round mdamp PLLN 214 MODCNT 100 Where fPLLIN represents the PLL input clock frequency fmod represents the spread spectrum...

Page 198: ...CK_PLLI2S CK_PLLI2SVCO PLLI2SDIV This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PLLDIGFSYSDIV 5 0 PLLDIGOSEL 1 0 Reserved PLLI2SPSC 2 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PLLI2SN 6 0 Reserved PLLI2SDIV 5 0 rw rw Bits Fields Descriptions 31 26 PLLDIGFSYSDIV 5 0 PLLDIG clock divider factor for system clock S...

Page 199: ...VCO is betw een 64MHz to 500MHz The value of PLLI2SN must 8 PLLI2SN 127 0000000 Reserved 0000001 Reserved 0000111 Reserved 0001000 CK_PLLI2SVCO CK_PLLI2SVCOSRC x 8 0001001 CK_PLLI2SVCO CK_PLLI2SVCOSRC x 9 1111111 CK_PLLI2SVCO CK_PLLI2SVCOSRC x 127 7 6 Reserved Must be kept at reset value 5 0 PLLI2SDIV 5 0 PLLI2S clock divider factor This bit is set and reset by softw are 000000 PLLI2SDIV input sou...

Page 200: ...as USART2 source clock 11 CK_IRC16M selected as USART2 source clock 27 26 I2C0SEL 1 0 I2C0 Clock Source Selection Set and reset by softw are to control the I2C0 clock source 00 CK_APB1 selected as I2C0 source clock 01 CK_SYS selected as I2C0 source clock 1x CK_IRC16M selected as I2C0 source clock 25 Reserved Must be kept at reset value 24 TIMERSEL TIMER clock selection This bit is set and reset by...

Page 201: ...lter Trust zone security by RF 0 LDO analog pow er dow n 1 LDO analog pow er on 16 RFPLLPU RFPLL pow er on enable Trust zone security by RF 0 RFPLL pow er dow n 1 RFPLL pow er on 15 RFPLLLOCK RF PLL LOCK 0 RFPLL is not Lock 1 RFPLL locked 14 RFPLLCALEN RF PLL Calculation enable Trust zone security by RF 0 RF PLL Calculation disable 1 RF PLL Calculation enable 13 12 Reserved Must be kept at reset v...

Page 202: ...der factor for I2S clock 000000 PLL clock divided by 1 for I2S clock 000001 PLL clock divided by 2 for I2S clock 111111 PLL clock divided by 64 for I2S clock 23 Reserved Must be kept at reset value 22 SDIOSEL 1 Bit 1 of SDIOSEL See bits 16 of RCU_ADDCTL 21 17 SDIODIV 4 0 SDIO clock divider factor This bit is set and reset by softw are 00000 SDIODIV input source clock divided by 1 00001 SDIODIV inp...

Page 203: ...rce clock 10 6 Reserved Must be kept at reset value 5 1 USBFSDIV 4 0 USBFS clock divider factor Division the PLL or PLLDIG clock for USBFS clock according to USBFSSEL bit 00000 USBFSDIV input source clock divided by 1 00001 USBFSDIV input source clock divided by 2 11111 USBFSDIV input source clock divided by 32 0 USBFSSEL USBFS clock selection Set and reset by softw are This bit used to generate U...

Page 204: ...2S configuration and status bits security protection Set and reset by softw are 0 Non secure 1 Secure 7 PLLDIGSECP PLLDIG configuration and status bits security protection Set and reset by softw are 0 Non secure 1 Secure 6 PLLSECP Main PLL configuration and status bits security protection Set and reset by softw are 0 Non secure 1 Secure 5 PRESCSECP AHBx APBx prescaler configuration bits security p...

Page 205: ...and non privileges This register provides security status of security configuration bits in RCU_SECP_CFG register When TZEN 0 this register is RAZ WI This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BKPSEC PF RMVFSE CF PLLI2SS ECPF PLLDIGS ECPF PLLSECP F PRESCS ECPF S...

Page 206: ...e 4 SYSCLKSECPF SYSCLK clock selection clock output on MCO configuration Set and reset by softw are 0 Non secure 1 Secure 3 LXTALSECPF LXTAL clock configuration and status bits security protection flag Set and reset by softw are 0 Non secure 1 Secure 2 IRC32KSECPF IRC32K clock configuration and status bits security protection flag Set and reset by softw are 0 Non secure 1 Secure 1 HXTALSECPF HXTAL...

Page 207: ...6 5 4 3 2 1 0 FMCSEC PF Reserved WIFISEC PF CRCSEC PF Reserved PCSECP F PBSECP F PASECP F r r r r r r Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 USBFSSECF USBFS security protection flag This flag is set by hardw are w hen it is secure 0 Non secure USBFS 1 Secure USBFS 28 23 Reserved Must be kept at reset value 22 DMA1SECF DMA1 security protection flag This flag is set b...

Page 208: ...security protection flag This flag is set by hardw are w hen it is secure 0 Non secure Wi Fi 1 Secure Wi Fi 12 CRCSECF CRC security protection flag This flag is set by hardw are w hen it is secure 0 Non secure CRC 1 Secure CRC 11 3 Reserved Must be kept at reset value 2 PCSECF GPIO port C security protection flag This flag is set by hardw are w hen it is secure 0 Non secure GPIO port C 1 Secure GP...

Page 209: ...0 Reserved TRNGSE CPF HAUSEC PF CAUSEC PF PKCAUS ECPF Reserved DCISECP F rw rw rw rw rw Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 TRNGSECPF TRNG security protection flag This flag is set by hardw are w hen it is secure 0 Non secure TRNG 1 Secure TRNG 5 HAUSECPF HAU security protection flag This flag is set by hardw are w hen it is secure 0 Non secure HAU 1 Secure HAU 4 C...

Page 210: ... 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved QSPISEC PF SQPISEC PF r r Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 QSPISECPF QSPI security protection flag This flag is set by hardw are w hen it is secure 0 Non secure QSPI 1 Secure QSPI 0 SQPISECPF SQPI security protection flag This flag is set by hardw are w hen it is secure 0 Non secure SQ...

Page 211: ...0 Non secure PMU 1 Secure PMU 27 23 Reserved Must be kept at reset value 22 I2C1SECPF I2C1 security protection flag This flag is set by hardw are w hen it is secure 0 Non secure I2C1 1 Secure I2C1 21 I2C0SECPF I2C0 security protection flag This flag is set by hardw are w hen it is secure 0 Non secure I2C0 1 Secure I2C0 20 19 Reserved Must be kept at reset value 18 USART0SECPF USART0 security prote...

Page 212: ...re w hen it is secure 0 Non secure TIMER3 1 Secure TIMER3 1 TIMER2SECPF TIMER2 security protection flag This flag is set by hardw are w hen it is secure 0 Non secure TIMER2 1 Secure TIMER2 0 TIMER1SECPF TIMER1 security protection flag This flag is set by hardw are w hen it is secure 0 Non secure TIMER 1 Secure TIMER1 6 5 32 APB2 secure protection status register RCU_APB2SECP_STAT Address offset 0x...

Page 213: ...PDF 1 Secure HPDF 29 19 Reserved Must be kept at reset value 18 TIMER16SECPF TIMER16 security protection flag This flag is set by hardw are w hen it is secure 0 Non secure TIMER16 1 Secure TIMER16 17 TIMER15SECPF TIMER15 security protection flag This flag is set by hardw are w hen it is secure 0 Non secure TIMER15 1 Secure TIMER15 16 15 Reserved Must be kept at reset value 14 SYSCFGSECPF SYSCFG se...

Page 214: ...protection flag This flag is set by hardw are w hen it is secure 0 Non secure TIMER0 1 Secure TIMER0 6 5 33 Voltage key register RCU_VKEY Address offset 0x100 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY 15 0 w Bits Fields Descriptions 31 0 K...

Page 215: ... 7 6 5 4 3 2 1 0 Reserved DSLPVS 1 0 rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 0 DSLPVS 1 0 Deep sleep mode voltage select These bits are set and reset by softw are 00 The core voltage is 1 1V in Deep sleep mode 01 The core voltage is 1 0V in Deep sleep mode 10 The core voltage is 0 9V in Deep sleep mode 11 The core voltage is 0 8V in Deep sleep mode ...

Page 216: ...y configuration 16 priority levels Efficient interrupt processing Support exception pre emption and tail chaining Wake up system from power saving mode Up to 29 independent edge detectors in EXTI Three trigger types rising falling and both edges Software interrupt or event trigger Trigger sources configurable Secure events The access to control and configuration bits of secure input events can be ...

Page 217: ...SV 14 Programmable 0x0000_0038 Pendable request for system service SysTick 15 Programmable 0x0000_003C System tick timer Note When the processor is without the Security Extension the priority of HardFault is 1 and vector address 0x0000_001C is reserved When TrustZone is enabled exception vector numbers 1 15 are banked or not between secure and non secure please refer to the corresponding kernel do...

Page 218: ...interrupt 0x0000_008C IRQ 20 36 RTC Tamper and TimeStamp events security interrupt 0x0000_0090 IRQ 21 37 RTC Wakeup event security interrupt 0x0000_0094 IRQ 22 38 RTC Alarm event security interrupt 0x0000_0098 IRQ 23 39 EXTI Line5 9 interrupt 0x0000_009C IRQ 24 40 TIMER0 Break interrupt 0x0000_00A0 IRQ 25 41 TIMER0 update interrupt 0x0000_00A4 IRQ 26 42 TIMER0 commutation interrupt 0x0000_00A8 IRQ...

Page 219: ..._0124 IRQ58 74 DMA1 channel2 global interrupt 0x0000_0128 IRQ59 75 DMA1 channel3 global interrupt 0x0000_012C IRQ60 76 DMA1 channel4 global interrupt 0x0000_0130 IRQ61 77 DMA1 channel5 global interrupt 0x0000_0134 IRQ62 78 DMA1 channel6 global interrupt 0x0000_0138 IRQ63 79 DMA1 channel7 global interrupt 0x0000_013C IRQ64 65 80 81 Reserved 0x0000_0140 0x0000_0144 IRQ66 82 Wi Fi11N w akeup interrup...

Page 220: ...0000_01C0 IRQ97 113 TSI global interrupt 0x0000_01C4 IRQ98 114 ICACHE global interrupt 0x0000_01C8 IRQ99 115 TZIAC security interrupt 0x0000_01CC IRQ100 116 FMC secure interrupt 0x0000_01D0 IRQ101 117 QSPI security interrupt 0x0000_01D4 7 4 External interrupt and event EXTI block diagram Figure 7 1 Block diagram of EXTI EXTILi ne0 28 E dge detect or P ol ari ty C ontrol S oftw are Tri gger Interru...

Page 221: ... for the processor to wake up the CPU from Deep sleep mode Both internal trigger lines can be masked by setting corresponding INTEN and EVEN registers in EXTI module Hardware Trigger Hardware trigger may be used to detect the voltage change of external or internal signals The software should follow these steps to use this function 1 Configure EXTI sources in SYSCFG module based on application requ...

Page 222: ... Wakeup event non secure 25 RTC Wakeup event secure 26 I2C0 Wakeup event 27 USART0 Wakeup 28 USART2 Wakeup 7 6 EXTI eventprotection The EXTI is able to protect event register bits from being modified by non secure and unprivileged accesses The protection can individually be activated per input event via the register bits in EXTI_SECCFG and EXTI_PRIVCFG At EXTI level the protection consists in prev...

Page 223: ...bits can only be modified and read by a secure access a non secure write access is discarded and a read returns 0 When input events are non secure the security is disabled The associated input event configuration and control bits can be modified and read by a secure access and non secure access The security configuration in registers EXTI_SECCFG can be globally locked after reset by EXTI_LOCK LOCK...

Page 224: ...et value 28 0 INTENx Interrupt enable bit x x 0 28 When EXTI_SECCFG SECx is disabled INTENx can be accessed w ith non secure and secure access When EXTI_SECCFG SECx is enabled INTENx can only be accessed w ith secure access Non secure w rite to this bit x is discarded non secure read returns 0 When EXTI_PRIVCFG PRIVx is disabled INTENx can be accessed w ith unprivileged and privilege access When E...

Page 225: ...rom Linex is enabled 7 9 3 Rising edge trigger enable register EXTI_RTEN Address offset 0x08 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RTEN28 RTEN27 RTEN26 RTEN25 RTEN24 RTEN23 RTEN22 RTEN21 RTEN20 RTEN19 RTEN18 RTEN17 RTEN16 rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTEN15 RTE...

Page 226: ...et value 28 0 FTENx Falling edge trigger enable x 0 28 When EXTI_SECCFG SECx is disabled FTENx can be accessed w ith non secure and secure access When EXTI_SECCFG SECx is enabled FTENx can only be accessed w ith secure access Nonsecure w rite to this bit x is discarded non secure read returns 0 When EXTI_PRIVCFG PRIVx is disabled FTENx can be accessed w ith unprivileged and privilege access When E...

Page 227: ... the EXTIx softw are interrupt event request 1 Activate the EXTIx softw are interrupt event request 7 9 6 Pending register EXTI_PD Address offset 0x14 Reset value undefined This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PD28 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_...

Page 228: ...3 SEC12 SEC11 SEC10 SEC9 SEC8 SEC7 SEC6 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 29 Reserved Must be kept at reset value 28 0 SECx Security enable on event input x w here x 0 to 28 When EXTI_PRIVCFG PRIVx is disabled SECx can be accessed w ith privilege and unprivileged access When EXTI_PRIVCFG PRIVx is enabled SECx can only be w rit...

Page 229: ...privilege disabled unprivileged 1 Event privilege enabled privileged 7 9 9 Lock register EXTI_LOCK Address offset 0x20 System reset 0x0000 0000 This register provides both write access security a non secure write access is ignored and a read access returns zero data and generate an illegal access event This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 230: ...e Each GPIO pin can be configured as pull up pull down or no pull up pull down All GPIOs are high current capable except for analog mode 8 2 Characteristics Input output direction control Schmitt trigger input function enable control Each pin weak pull up pull down function Output push pull open drain enable control Output set reset control External interrupt with programmable trigger edge using E...

Page 231: ...ll up 01 pull dow n 10 GPIO OUTPUT push pull Floating 01 0 00 pull up 01 pull dow n 10 open drain Floating 1 00 pull up 01 pull dow n 10 AFIO INPUT X Floating 10 X 00 pull up 01 pull dow n 10 AFIO OUTPUT push pull Floating 10 0 00 pull up 01 pull dow n 10 open drain Floating 1 00 pull up 01 pull dow n 10 ANALOG X X 11 X XX Figure 8 1 Basic structure of a standard I O port bit shows the basic struc...

Page 232: ... the external pins can be captured at every AHB clock cycle to the port input status register GPIOx_ISTAT When the GPIO pins are configured as output pins user can configure the speed of the ports And chooses the output driver mode Push Pull or Open Drain mode The value of the port output control register GPIOx_OCTL is output on the I O pin There is no need to read then write when programming the ...

Page 233: ...hestandard GPIO registers When for ADC or DAC additional functions the port must be configured as analog mode When for RTC WKUPx and oscillators additional functions the port type is set automatically by related RTC PMU and RCU registers These ports can be used as normal GPIO when the additional functions disabled 8 3 5 Input configuration When GPIO pin is configured as Input The schmitt trigger i...

Page 234: ... last writtenvalue A read access to the port input status register gets theI O state Figure 8 3 Output configuration shows the output configuration Figure 8 3 Output configuration 8 3 7 Analog configuration When GPIO pin is used as analog configuration The weak pull up and pull down resistors are disabled The output buffer is disabled The schmitt trigger input is disabled The port input status reg...

Page 235: ...tored into the port input status register every AHB clock A read access to the port input status register gets theI O state A read access to the port output control register gets the last writtenvalue Figure 8 5 Alternate function configuration shows the alternate function configuration Figure 8 5 Alternate function configuration 8 3 9 GPIO locking function The locking mechanism allows the IO conf...

Page 236: ...reGPIOpin securestate onceonepinset tosecureitscorrespondingconfiguration bits for alternate function control bits mode selection reset set bits lock bits I O data are secure Table 8 2 GPIO secure state show GPIO secure state Table 8 2 GPIOsecure state GPIOx_SCFG Register Bit Bits Secure state SCFGy 1 GPIOx_CTL CTLy 1 0 Non secure read is zero w rite w ill ignore GPIOx_OMODE OMy GPIOx_OSPD OSPDy 1...

Page 237: ...ey 1 0 default value is 00 Please refer to the table Table 8 3 GPIOx_CTL reset value below for this register reset value Table 8 3 GPIOx_CTL reset value FW AES Key 1 0 GPIOA_CTL GPIOB_CTL GPIOC_CTL 00 0xA800 0000 0x0000 0280 0x0000 0000 01 0xA800 AA00 0x0000 0280 0x0000 0000 10 0xAAA8 0000 0x0000 0280 0x0000 0A00 11 0xAAA8 AA00 0x0000 0280 0x0000 0A00 This register has to be accessed by word 32 bi...

Page 238: ... CTL0 1 0 description 17 16 CTL8 1 0 Pin 8 configuration bits These bits are set and cleared by softw are refer to CTL0 1 0 description 15 14 CTL7 1 0 Pin 7 configuration bits These bits are set and cleared by softw are refer to CTL0 1 0 description 13 12 CTL6 1 0 Pin 6 configuration bits These bits are set and cleared by softw are refer to CTL0 1 0 description 11 10 CTL5 1 0 Pin 5 configuration b...

Page 239: ...22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OM15 OM14 OM13 OM12 OM11 OM10 OM9 OM8 OM7 OM6 OM5 OM4 OM3 OM2 OM1 OM0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 OM15 Pin 15 output mode bit These bits are set and cleared by softw are refer to OM0 description 14 OM14 Pin 14 output mode bit These bits are ...

Page 240: ...ts are set and cleared by softw are refer to OM0 description 5 OM5 Pin 5 output mode bit These bits are set and cleared by softw are refer to OM0 description 4 OM4 Pin 4 output mode bit These bits are set and cleared by softw are refer to OM0 description 3 OM3 Pin 3 output mode bit These bits are set and cleared by softw are refer to OM0 description 2 OM2 Pin 2 output mode bit These bits are set a...

Page 241: ...his register has to be accessed by word 32 bit half word 16 bit byte 8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OSPD15 1 0 OSPD14 1 0 OSPD13 1 0 OSPD12 1 0 OSPD11 1 0 OSPD10 1 0 OSPD9 1 0 OSPD8 1 0 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSPD7 1 0 OSPD6 1 0 OSPD5 1 0 OSPD4 1 0 OSPD3 1 0 OSPD2 1 0 OSPD1 1 0 OSPD0 1 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions ...

Page 242: ...OSPD0 1 0 description 11 10 OSPD5 1 0 Pin 5 output max speed bits These bits are set and cleared by softw are refer to OSPD0 1 0 description 9 8 OSPD4 1 0 Pin 4 output max speed bits These bits are set and cleared by softw are refer to OSPD0 1 0 description 7 6 OSPD3 1 0 Pin 3 output max speed bits These bits are set and cleared by softw are refer to OSPD0 1 0 description 5 4 OSPD2 1 0 Pin 2 outpu...

Page 243: ...is register has to be accessed by word 32 bit half word 16 bit byte 8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PUD15 1 0 PUD14 1 0 PUD13 1 0 PUD12 1 0 PUD11 1 0 PUD10 1 0 PUD9 1 0 PUD8 1 0 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PUD7 1 0 PUD6 1 0 PUD5 1 0 PUD4 1 0 PUD3 1 0 PUD2 1 0 PUD1 1 0 PUD0 1 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 PUD15 1 0 P...

Page 244: ...0 1 0 description 11 10 PUD5 1 0 Pin 5 pull up or pull dow n bits These bits are set and cleared by softw are refer to PUD0 1 0 description 9 8 PUD4 1 0 Pin 4 pull up or pull dow n bits These bits are set and cleared by softw are refer to PUD0 1 0 description 7 6 PUD3 1 0 Pin 3 pull up or pull dow n bits These bits are set and cleared by softw are refer to PUD0 1 0 description 5 4 PUD2 1 0 Pin 2 p...

Page 245: ...in input status y 0 15 These bits are set and cleared by hardw are 0 Input signal low 1 Input signal high 8 5 6 Port output control register GPIOx_OCTL x A C Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit half word 16 bit byte 8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OCTL15 OCTL14 OCTL13 OCTL12...

Page 246: ...Clear bit y y 0 15 These bits are set and cleared by softw are 0 No action on the corresponding OCTLy bit 1 Clear the corresponding OCTLy bit to 0 15 0 BOPy Pin Set bit y y 0 15 These bits are set and cleared by softw are 0 No action on the corresponding OCTLy bit 1 Set the corresponding OCTLy bit to 1 8 5 8 Port configuration lock register GPIOx_LOCK x A C Address offset 0x1C Reset value 0x0000 0...

Page 247: ...A5 PA6 PA7 PB3 PB4 is configured as one set of QSPI port automatically by the hardware and when the bit1 is 1 the PA9 PA10 PA11 PA12 PC4 PC5 is configured as the other set of QSPI port automatically by the hardware as well FW AES Key 1 0 default value is 00 Please refer to the table Table 8 6 GPIOx_AFSEL0 reset value below for this register reset value Table 8 6 GPIOx_AFSEL0 reset value FW AES Key...

Page 248: ...y softw are refer to SEL0 3 0 description 3 0 SEL0 3 0 Pin 0 alternate function selected These bits are set and cleared by softw are 0000 AF0 selected reset value 0001 AF1 selected 0010 AF2 selected 0011 AF3 selected 1111 AF15 selected 8 5 10 Alternate function selected register 1 GPIOx_AFSEL1 x A C Address offset 0x24 Reset value The reset value is determined by the FW AES Key bit0 and bit1 in th...

Page 249: ...by softw are refer to SEL8 3 0 description 23 20 SEL13 3 0 Pin 13 alternate function selected These bits are set and cleared by softw are refer to SEL8 3 0 description 19 16 SEL12 3 0 Pin 12 alternate function selected These bits are set and cleared by softw are refer to SEL8 3 0 description 15 12 SEL11 3 0 Pin 11 alternate function selected These bits are set and cleared by softw are refer to SEL...

Page 250: ...r bit y y 0 15 These bits are set and cleared by softw are 0 No action on the corresponding OCTLy bit 1 Clear the corresponding OCTLy bit 8 5 12 Port bit toggle register GPIOx_TG x A C Address offset 0x2C Reset value 0x0000 0000 This register has to be accessed by word 32 bit half word 16 bit byte 8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 251: ...word 32 bit half word 16 bit byte 8 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCFG15 SCFG14 SCFG13 SCFG12 SCFG11 SCFG10 SCFG9 SCFG8 SCFG7 SCFG6 SCFG5 SCFG4 SCFG3 SCFG2 SCFG1 SCFG0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 SCFGy y 0 15 GPIOx secure configure bit Th...

Page 252: ...h is configured by the TZBMPC through an AHB interface TZIAC is used to enable all illegal access events for slave master peripherals in system If an interrupt is enabled a dedicated interrupt signal is asserted and generates a secure interrupt towards NVIC whenever a security violation is detected The interrupt is cleared by writing to the appropriate register of TZIAC 9 2 Characteristics TZSPC T...

Page 253: ...e union function of TrustZone protection controller which is beyondAHB andARMv8 M These beyond functions are realized through APB TrustZone peripheral protection controller PTZPPC in AHB APB bridge gates transactions to and responses from securable APB peripherals when a security violation occurs AHB TrustZone peripheral protection controller HTZPPC inAHB address decode gates transactions to and r...

Page 254: ... theyareTrustZone awareperipherals for more information please refer to the security protection description of TrustZone aware peripherals Illegal non privilege access If a privilege resource is accessed by a non privilege resource this will be considered as illegal but for this illegal access there is no event or bus error will generate read access will return zero write access will be ignored Me...

Page 255: ...rwise a privileged transaction non secure is sufficient The definition of these privilege attributes is available even when TZEN 0 The secure configuration bit of given peripheral can be modified only with a secure privilege transaction if the peripheral has been configured as privilege otherwise a secure transaction non privileged is sufficient For external memories SQPI_PSRAM 128MB or QSPI_FLASH...

Page 256: ...ock 32 blocks of SRAM base block size On the devices if the SRAM size is 64 Kbytes and the block size is 256 bytes then union block size is 32 256 8 Kbytes and 64 8 1 is 7 means y is 0 7 It means 8 vector registers 32 bit are needed and 8 bit lock register is needed Table 9 3 TZBMPCx describes the characteristics of the available TZBMPCx Table 9 3 TZBMPCx MPC Block Number of blocks y Kind of memor...

Page 257: ...the signals is set according to the security protection SPC level and TZPCU_TZSPC_DBG_CFG register security protection level has a high priority The reset value of DBGEN NIDEN SPIDEN and SPNIDEN is 1 If TZEN 0 DBGEN and NIDEN are automatically set to 1 and SPIDEN and SPNIDEN are automatically set to 0 If TZEN 1 then DBGEN NIDEN SPIDEN and SPNIDEN are configured through the secure register The DBGP...

Page 258: ... kept at reset value 0 LK TZSPC items lock configuration bit This bit is set and cleared by softw are 0 control register not locked 1 control register locked Note This bit is unset by default and once set it can not be reset until global TZSPC reset 9 4 2 TZSPC secure access mode configuration register 0 TZPCU_TZSPC_SAM_CFG0 Address offset 0x10 Reset value 0x0000 0000 Secure write access only If a...

Page 259: ...nfigure TIMER0 secure access mode to non secure 1 Configure TIMER0 secure access mode to secure 29 27 Reserved Must be kept at reset value 26 USBFSSAM USBFS secure access mode configuration bit This bit is set and cleared by softw are 0 Configure USBFS secure access mode to non secure 1 Configure USBFS secure access mode to secure 25 16 Reserved Must be kept at reset value 15 I2C1SAM I2C1 secure a...

Page 260: ...n secure 1 Configure WWDGT secure access mode to secure 5 Reserved Must be kept at reset value 4 TIMER5SAM TIMER5 secure access mode configuration bit This bit is set and cleared by softw are 0 Configure TIMER5 secure access mode to non secure 1 Configure TIMER5 secure access mode to secure 3 TIMER4SAM TIMER4 secure access mode configuration bit This bit is set and cleared by softw are 0 Configure...

Page 261: ...10 9 8 7 6 5 4 3 2 1 0 PKCAUS AM TRNGSA M HAUSAM CAUSAM ADCSAM ICACHES AM TSISAM CRCSAM HPDFSA M Reserved TIMER16 SAM TIMER15 SAM Reserved USART0 SAM Reserved rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 17 Reserved Must be kept at reset value 16 SDIOSAM SDIO secure access mode configuration bit This bit is set and cleared by softw are 0 Configure SDIO secure access mode to non ...

Page 262: ...oftw are 0 Configure TSI secure access mode to non secure 1 Configure TSI secure access mode to secure 8 CRCSAM CRC secure access mode configuration bit This bit is set and cleared by softw are 0 Configure CRC secure access mode to non secure 1 Configure CRC secure access mode to secure 7 HPDFSAM HPDF secure access mode configuration bit This bit is set and cleared by softw are 0 Configure HPDF se...

Page 263: ... by privilege secure code Read accesses are not limited This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WIFISAM DCISAM I2S1_AD DSAM WIFI_RF SAM QSPI_FL ASHREG SAM SQPI_PS RAMREG SAM Reserved EFUSES AM Reserved rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits Fields Descriptions 31 WIFISAM Wi Fi secure access mode configuration...

Page 264: ...flash register secure access mode to secure 25 24 Reserved Must be kept at reset value 23 EFUSESAM EFUSE register secure access mode configuration bit This bit is set and cleared by softw are 0 Configure EFUSE register secure access mode to non secure 1 Configure EFUSE register secure access mode to secure 22 0 Reserved Must be kept at reset value 9 4 5 TZSPC privilege access mode configuration re...

Page 265: ...privilege access mode to non privilege 1 Configure USBFS privilege access mode to privilege 25 16 Reserved Must be kept at reset value 15 I2C1PAM I2C1 privilege access mode configuration bit This bit is set and cleared by softw are 0 Configure I2C1 privilege access mode to non privilege 1 Configure I2C1 privilege access mode to privilege 14 I2C0PAM I2C0 privilege access mode configuration bit This...

Page 266: ...rivilege 1 Configure TIMER5 privilege access mode to privilege 3 TIMER4PAM TIMER4 privilege access mode configuration bit This bit is set and cleared by softw are 0 Configure TIMER4 privilege access mode to non privilege 1 Configure TIMER4 privilege access mode to privilege 2 TIMER3PAM TIMER3 privilege access mode configuration bit This bit is set and cleared by softw are 0 Configure TIMER3 privil...

Page 267: ...vilege access mode configuration bit This bit is set and cleared by softw are 0 Configure SDIO privilege access mode to non privilege 1 Configure SDIO privilege access mode to privilege 15 PKCAUPAM PKCAU privilege access mode configuration bit This bit is set and cleared by softw are 0 Configure PKCAU privilege access mode to non privilege 1 Configure PKCAU privilege access mode to privilege 14 TR...

Page 268: ...1 Configure CRC privilege access mode to privilege 7 HPDFPAM HPDF privilege access mode configuration bit This bit is set and cleared by softw are 0 Configure HPDF privilege access mode to non privilege 1 Configure HPDF privilege access mode to privilege 6 5 Reserved Must be kept at reset value 4 TIMER16PAM TIMER16 privilege access mode configuration bit This bit is set and cleared by softw are 0 ...

Page 269: ...SEP AM Reserved rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits Fields Descriptions 31 WIFIPAM Wi Fi privilege access mode configuration bit This bit is set and cleared by softw are 0 Configure Wi Fi privilege access mode to non privilege 1 Configure Wi Fi privilege access mode to privilege 30 DCIPAM DCI privilege access mode configuration bit This bit is set and cleare...

Page 270: ...PA M EFUSE register privilege access mode configuration bit This bit is set and cleared by softw are 0 Configure EFUSE register privilege access mode to non privilege 1 Configure EFUSE register privilege access mode to privilege 22 0 Reserved Must be kept at reset value 9 4 8 TZSPC external memory x non secure mark register 0 TZPCU_TZSPC_TZMMPCx_NSM0 Address offset 0x030 0x010 x x 0 to 1 Reset val...

Page 271: ... secure 9 4 9 TZSPC external memory x non secure mark register 1 TZPCU_TZSPC_TZMMPCx_NSM1 Address offset 0x034 0x010 x x 0 to 1 Reset value 0x0000 0000 If TZEN 1 the given reset value is valid If TZEN 0 the reset value is 0x4000 0000 Secure access only NOTE When NSM1_SADD NSM1_LEN is over the maximum size of the memory NSM1_LEN will set a constrainedmaximum Every TZPCU_TZMMPCx_NSMy y 0 3 register ...

Page 272: ...ister 2 TZPCU_TZSPC_TZMMPCx_NSM2 Address offset 0x038 0x010 x x 0 Reset value 0x0000 0000 If TZEN 1 the given reset value is valid If TZEN 0 the reset value is 0x4000 0000 Secure access only NOTE When NSM2_SADD NSM2_LEN is over the maximum size of the memory NSM2_LEN will set a constrainedmaximum Every TZPCU_TZMMPCx_NSMy y 0 3 register can define a non secure area of the memory the whole non secur...

Page 273: ...010 x x 0 Reset value 0x0000 0000 If TZEN 1 the given reset value is valid If TZEN 0 the reset value is 0x4000 0000 Secure access only NOTE When NSM3_SADD NSM3_LEN is over the maximum size of the memory NSM3_LEN will set a constrainedmaximum Every TZPCU_TZMMPCx_NSMy y 0 3 register can define a non secure area of the memory the whole non secure area of the memory is the union of these areas If NSM0...

Page 274: ...200 Reset value 0x0000 000F Secure write access only If TZEN 1 the given reset value is valid If TZEN 0 the reset value is 0x0000 0003 If DBGPAM bit in TZPCU_TZSPC_PAM_CFG is not set this register can be written by non privilege secure code If DBGPAM bit in TZPCU_TZSPC_PAM_CFG is set this register can be written only by privilege secure code Read accesses are not limited This register has to be ac...

Page 275: ... access base address 0x500A 0800 TZBMPC0 non secure access base address 0x400A 0800 9 5 1 TZBMPC0 control register TZPCU_TZBMPC0_CTL Address offset 0x000 Reset value 0x0000 0000 Secure access only This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRWACF G SECSTAT CFG Reserved rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LK rw Bits Fields Descri...

Page 276: ...FFFF FFFF If TZEN 1 the given reset value is valid If TZEN 0 the reset value is 0x0000 0000 Secure access only This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 B 31 32 y B 30 32 y B 29 32 y B 28 32 y B 27 32 y B 26 32 y B 25 32 y B 24 32 y B 23 32 y B 22 32 y B 21 32 y B 20 32 y B 19 32 y B 18 32 y B 17 32 y B 16 32 y rw rw rw rw rw rw rw rw rw rw rw ...

Page 277: ...blocks 0 to 7 secure access mode lock configuration bits These bits are set and cleared by softw are 0x0000 0000 security configuration unlocked for all union blocks 0x0000 0001 security configuration locked only for union blocks 0 0x0000 000F security configuration locked for all union blocks of SRAM0 9 6 TZBMPC1 registersdefinition TZBMPC1 secure access base address 0x500A 0C00 TZBMPC1 non secur...

Page 278: ...ed by softw are 0 Not lock control registe of the TZBMPC sub block 1 Lock control registe of the TZBMPC sub block Note This bit is unset by default and once set it can not be reset until next reset 9 6 2 TZBMPC1 vector register y TZPCU_TZBMPC1_VECy Address offset 0x100 0x04 y y 0 to 7 Reset value 0xFFFF FFFF If TZEN 1 the given reset value is valid If TZEN 0 the reset value is 0x0000 0000 Secure a...

Page 279: ...ved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LKUB7 LKUB6 LKUB5 LKUB4 LKUB3 LKUB2 LKUB1 LKUB0 rwo rwo rwo rwo rwo rwo rwo rwo Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 LKUB 7 0 The union blocks 0 to 7 secure access mode lock configuration bits These bits are set and cleared by softw are 0x0000 0000 security configuration unlocked for all union blocks 0x0000 0001 s...

Page 280: ...ecure 1 Configure TZBMPC source clock still to secure if there do not exists secure area in TZBMPC 29 1 Reserved Must be kept at reset value 0 LK The control register of the TZBMPC sub block lock configuration bit This bit is set and cleared by softw are 0 Not lock control registe of the TZBMPC sub block 1 Lock control registe of the TZBMPC sub block Note This bit is unset by default and once set ...

Page 281: ...ed by word 32 bit Software can only write once to this bit and can also read it at any time Only a reset can return the bit to its reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LKUB15 LKUB14 LKUB13 LKUB12 LKUB11 LKUB10 LKUB9 LKUB8 LKUB7 LKUB6 LKUB5 LKUB4 LKUB3 LKUB2 LKUB1 LKUB0 rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo ...

Page 282: ...CFG Security state configuration bit This bit is set and cleared by softw are 0 Configure TZBMPC source clock to non secure if there do not exists secure area in TZBMPC if exits secure area then TZBMPC source clock is secure 1 Configure TZBMPC source clock still to secure if there do not exists secure area in TZBMPC 29 1 Reserved Must be kept at reset value 0 LK The control register of the TZBMPC ...

Page 283: ...x0000 0001 only blocks 0 of union block y are secure 0xFFFF FFFF all union blocks are secure 9 8 3 TZBMPC3 lock register 0 TZPCU_TZBMPC3_LOCK0 Address offset 0x010 Reset value 0x0000 0000 Secure access only This register has to be accessed by word 32 bit Software can only write once to this bit and can also read it at any time Only a reset can return the bit to its reset value 31 30 29 28 27 26 25...

Page 284: ...E Reserved USBFSIE Reserved rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2C1IE I2C0IE Reserved USART2I E USART1I E Reserved SPI1IE FWDGTI E WWDGTI E Reserved TIMER5I E TIMER4I E TIMER3I E TIMER2I E TIMER1I E rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 SPI0IE SPI0 illegal access interrupt enable bit This bit is set and cleared by softw are 0 Disable SPI0 illegal access interr...

Page 285: ...rupt enable bit This bit is set and cleared by softw are 0 Disable USART1 illegal access interrupt 1 Enable USART1 illegal access interrupt 9 Reserved Must be kept at reset value 8 SPI1IE SPI1 illegal access interrupt enable bit This bit is set and cleared by softw are 0 Disable SPI1 illegal access interrupt 1 Enable SPI1 illegal access interrupt 7 FWDGTIE FWDGT illegal access interrupt enable bit...

Page 286: ...al access interrupt 1 Enable TIMER1 illegal access interrupt 9 9 2 TZIAC interrupt enable register 1 TZPCU_TZIAC_INTEN1 Address offset 0x004 Reset value 0x0000 0000 Secure access only This register is used to enable disable illegal access event for each source This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved EXTIIE FMCIE FLASHIE RCUIE Reserve...

Page 287: ...illegal access interrupt 1 Enable DMA1 illegal access interrupt 22 DMA0IE DMA0 illegal access interrupt enable bit This bit is set and cleared by softw are 0 Disable DMA0 illegal access interrupt 1 Enable DMA0 illegal access interrupt 21 SYSCFGIE SYSCFG illegal access interrupt enable bit This bit is set and cleared by softw are 0 Disable SYSCFG illegal access interrupt 1 Enable SYSCFG illegal acc...

Page 288: ...CAU illegal access interrupt 11 ADCIE ADC illegal access interrupt enable bit This bit is set and cleared by softw are 0 Disable ADC illegal access interrupt 1 Enable ADC illegal access interrupt 10 ICACHEIE ICACHE illegal access interrupt enable bit This bit is set and cleared by softw are 0 Disable ICACHE illegal access interrupt 1 Enable ICACHE illegal access interrupt 9 TSIIE TSI illegal acces...

Page 289: ...rupt enable register 2 TZPCU_TZIAC_INTEN2 Address offset 0x008 Reset value 0x0000 0000 Secure access only This register is used to enable disable illegal access event for each source This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WIFIIE DCIIE I2S1_AD DIE WIFI_RFI E QSPI_FL ASHREGI E SQPI_PS RAMREG IE QSPI_FL ASHIE SQPI_PS RAMIE EFUSEIE Reserved rw r...

Page 290: ...isable SQPI_PSRAMREG illegal access interrupt 1 Eisable SQPI_PSRAMREG illegal access interrupt 25 QSPI_FLASHIE QSPI FLASH illegal access interrupt enable bit This bit is set and cleared by softw are 0 Disable QSPI FLASH illegal access interrupt 1 Eisable QSPI FLASH illegal access interrupt 24 SQPI_PSRAMIE SQPI PSRAM illegal access interrupt enable bit This bit is set and cleared by softw are 0 Dis...

Page 291: ...isable SRAM1 illegal access interrupt 1 Eisable SRAM1 illegal access interrupt 5 TZBMPC0_REGIE TZBMPC0 REG illegal access interrupt enable bit This bit is set and cleared by softw are 0 Disable TZBMPC0 REG illegal access interrupt 1 Eisable TZBMPC0 REG illegal access interrupt 4 SRAM0IE SRAM0 illegal access interrupt enable bit This bit is set and cleared by softw are 0 Disable SRAM0 illegal acces...

Page 292: ...ss event 1 TIMER0 illegal access event pending 29 27 Reserved Must be kept at reset value 26 USBFSIAF USBFS illegal access event flag bit 0 no USBFS illegal access event 1 USBFS illegal access event pending 25 16 Reserved Must be kept at reset value 15 I2C1IAF I2C1 illegal access flag bit This bit is set and cleared by softw are 0 Disable I2C1 illegal access interrupt 1 Enable I2C1 illegal access ...

Page 293: ...nding 3 TIMER4IAF TIMER4 illegal access event flag bit 0 no TIMER4 illegal access event 1 TIMER4 illegal access event pending 2 TIMER3IAF TIMER3 illegal access event flag bit 0 no TIMER3 illegal access event 1 TIMER3 illegal access event pending 1 TIMER2IAF TIMER2 illegal access event flag bit 0 no TIMER2 illegal access event 1 TIMER2 illegal access event pending 0 TIMER1IAF TIMER1 illegal access ...

Page 294: ... access event pending 25 RCUIAF RCU illegal access event flag bit 0 no RCU illegal access event 1 RCU illegal access event pending 24 Reserved Must be kept at reset value 23 DMA1IAF DMA1 illegal access event flag bit 0 no DMA1 illegal access event 1 DMA1 illegal access event pending 22 DMA0IAF DMA0 illegal access event flag bit 0 no DMA0 illegal access event 1 DMA0 illegal access event pending 21 ...

Page 295: ...t 1 ADC illegal access event pending 10 ICACHEIAF ICACHE illegal access event flag bit 0 no ICACHE illegal access event 1 ICACHE illegal access event pending 9 TSIIAF TSI illegal access event flag bit 0 no TSI illegal access event 1 TSI illegal access event pending 8 CRCIAF CRC illegal access event flag bit 0 no CRC illegal access event 1 CRC illegal access event pending 7 HPDFIAF HPDF illegal acc...

Page 296: ...IA F SRAM3IA F TZBMPC 2_REGIA F SRAM2IA F TZBMPC 1_REGIA F SRAM1IA F TZBMPC 0_REGIA F SRAM0IA F Reserved TZIACIAF TZSPCIA F r r r r r r r r r r Bits Fields Descriptions 31 WIFIIAF Wi Fi illegal access event flag bit 0 No Wi Fi illegal access event 1 Wi Fi illegal access event pending 30 DCIIAF DCI illegal access event flag bit 0 no DCI illegal access event 1 DCI illegal access event pending 29 I2S...

Page 297: ...3 REG illegal access event pending 10 SRAM3IAF SRAM3 illegal access event flag bit 0 no SRAM3 illegal access event 1 SRAM3 illegal access event pending 9 TZBMPC2_REGIAF TZBMPC2 REG illegal access event flag bit 0 no TZBMPC2 REG illegal access event 1 TZBMPC2 REG illegal access event pending 8 SRAM2IAF SRAM2 illegal access event flag bit 0 no SRAM2 illegal access event 1 SRAM2 illegal access event ...

Page 298: ...erved USBFSIA FC Reserved w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2C1IAFC I2C0IAFC Reserved USART2I AFC USART1I AFC Reserved SPI1IAFC FWDGTI AFC WWDGTI AFC Reserved TIMER5I AFC TIMER4I AFC TIMER3I AFC TIMER2I AFC TIMER1I AFC w w w w w w w w w w w w Bits Fields Descriptions 31 SPI0IAFC SPI0 illegal access flag clear bit This bit is set by softw are 0 No action 1 Clear SPI0 illegal access flag ...

Page 299: ...w are 0 No action 1 Clear USART1 illegal access flag 9 Reserved Must be kept at reset value 8 SPI1IAFC SPI1 illegal access flag clear bit This bit is set by softw are 0 No action 1 Clear SPI1 illegal access flag 7 FWDGTIAFC FWDGT illegal access flag clear bit This bit is set by softw are 0 No action 1 Clear FWDGT illegal access flag 6 WWDGTIAFC WWDGT illegal access flag clear bit This bit is set b...

Page 300: ...Secure access only This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved EXTIIAFC FMCIAFC FLASHIA FC RCUIAFC Reserved DMA1IAF C DMA0IAF C SYSCFGI AFC PMUIAFC RTCIAFC Reserved SDIOIAF C w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PKCAUIA FC TRNGIAF C HAUIAFC CAUIAFC ADCIAFC ICACHEI AFC TSIIAFC CRCIAFC HPDFIAF C Reserved TIMER16I AFC TIM...

Page 301: ...lear bit This bit is set by softw are 0 No action 1 Clear DMA0 illegal access flag 21 SYSCFGIAFC SYSCFG illegal access flag clear bit This bit is set by softw are 0 No action 1 Clear SYSCFG illegal access flag 20 PMUIAFC PMU illegal access flag clear bit This bit is set by softw are 0 No action 1 Clear PMU illegal access flag 19 RTCIAFC RTC illegal access flag clear bit This bit is set by softw ar...

Page 302: ... No action 1 Clear ADC illegal access flag 10 ICACHEIAFC ICACHE illegal access flag clear bit This bit is set by softw are 0 No action 1 Clear ICACHE illegal access flag 9 TSIIAFC TSI illegal access flag clear bit This bit is set by softw are 0 No action 1 Clear TSI illegal access flag 8 CRCIAFC CRC illegal access flag clear bit This bit is set by softw are 0 No action 1 Clear CRC illegal access f...

Page 303: ...4 23 22 21 20 19 18 17 16 WIFIIAFC DCIIAFC I2S1_AD DIAFC WIFI_RFI AFC QSPI_FL ASHIAFC SQPI_PS RAMIAFC QSPI_FL ASHIAFC SQPI_PS RAMIAFC EFUSEIA FC Reserved w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TZBMPC 3_REGIA FC SRAM3IA FC TZBMPC 2_REGIA FC SRAM2IA FC TZBMPC 1_REGIA FC SRAM1IA FC TZBMPC 0_REGIA FC SRAM0IA FC Reserved TZIACIAF C TZSPCIA FC w w w w w w w w w w Bits Fields De...

Page 304: ...oftw are 0 No action 1 Clear QSPI FLASH illegal access flag 24 SQPI_PSRAMIAFC SQPI PSRAM illegal access flag clear bit This bit is set by softw are 0 No action 1 Clear SQPI PSRAM illegal access flag 23 EFUSEIAFC EFUSE illegal access flag clear bit This bit is set by softw are 0 No action 1 Clear EFUSE illegal access flag 22 12 Reserved Must be kept at reset value 11 TZBMPC3_REGIAFC TZBMPC3 REG ill...

Page 305: ...Clear SRAM1 illegal access flag 5 TZBMPC0_REGIAFC TZBMPC0 REG illegal access flag clear bit This bit is set by softw are 0 No action 1 Clear TZBMPC0 REG illegal access flag 4 SRAM0IAFC SRAM0 illegal access flag clear bit This bit is set by softw are 0 No action 1 Clear SRAM0 illegal access flag 3 2 Reserved Must be kept at reset value 1 TZIACIAFC TZIAC illegal access flag clear bit This bit is set...

Page 306: ... 4 AHB clock cycles for 32 bit input data size from data entered to the calculation result available Free 8 bit register is unrelated to calculationand can be used for any other goals by any other peripheral devices Fixed polynomial 0x4C11DB7 X32 X26 X23 X22 X16 X12 X11 X10 X8 X7 X5 X4 X2 X 1 This 32 bit CRC polynomial is a commonpolynomial used in Ethernet Figure 10 1 Block diagram of CRC calcula...

Page 307: ... by software setting the CRC_CTL register the new input raw data will be calculated based on the result of previous value of CRC_DATA CRC calculationwill spend4AHB clockcyclesfor32 bit datasize duringthis period AHB will not be hanged because of the existence of the 32 bit input buffer This module supplies an 8 bit free register CRC_FDATA CRC_FDATA is unrelated to the CRC calculation any value you...

Page 308: ... DATA 31 0 CRC calculation result bits Softw are w rites and reads This register is used to calculate new data and the register can be w ritten the new data directly Written value cannot be read because the read value is the previous CRC calculation result 10 4 2 Free data register CRC_FDATA Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 ...

Page 309: ...et 0x08 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RST rs Bits Fields Descriptions 31 1 Reserved Must be kept at reset value 0 RST Set this bit can reset the CRC_DATA register to the value of 0xFFFFFFFF then automatically cleared itself to 0 by hardw are This bit w i...

Page 310: ...the chip power consumption 32 bit random value seed is generated from analog noise so the random number is a true random number 11 3 Function overview Figure 11 1 TRNG blockdiagram AHB 32 bit Bus TRNG_CTL TRNG_STAT TRNG_DATA LFSR Clock Check Analog Seed TRNG_CLK Seed Check HCLK The random number seed comes from analog circuit This analog seed is then plugged into a linear feedback shift register L...

Page 311: ...N bit 3 When an interrupt occurs check the status register TRGN_STAT if SEIF 0 CEIF 0 and DRDY 1 then the random value in the data register could be read As required by the FIPS PUB 140 2 the first random data in data register should be saved but not be used Every subsequent new random data should be compared to the previously random data The data can only be used if it is not equal to the previou...

Page 312: ...tions 31 4 Reserved Must be kept at reset value 3 IE Interrupt enabled bit This bit controls the generation of an interrupt w hen DRDY SEIF or CEIF w as set 0 disable TRNG interrupt 1 enable TRNG interrupt 2 TRNGEN TRNG enabled bit 0 disable TRNG module reduce pow er consuming 1 enable TRNG module 1 0 Reserved Must be kept at reset value 11 4 2 Status register TRNG_STAT Address offset 0x04 Reset v...

Page 313: ...efore but now is recovered 1 Seed error is detected at current time if more than 64 consecutive same bits or more than 32 consecutive 01 or 10 changing are detected 1 CECS Clock error current status 0 Clock error is not detected at current time In case of CEIF 1 and CECS 0 it means clock error has been detected before but now is recovered 1 Clock error is detected at current time TRNG_CLK frequenc...

Page 314: ...GD32W51x User Manual 314 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRNDATA 15 0 r Bits Fields Descriptions 31 0 TRNDATA 31 0 32 bit random data ...

Page 315: ...ation mechanism is implemented to solve the competition between these two masters When the same peripheral is targeted the MCU access will be suspended for some specific bus cycles A round robinschedulingalgorithm isutilizedinthebus matrixtoguaranty at least half the bandwidth to the MCU 12 2 Characteristics Two AHB master interface for transferring data and one AHB slave interface for programming...

Page 316: ... enable and clear 12 3 Block diagram Figure 12 1 Block diagram of DMA Memory arbiter Memory Port Peripheral Port DMA Configuration Peripheral arbiter Peripheral control data MUX Memory control data MUX FIFO Channel 0 Channel 1 Channel 2 Channel 7 Memory control state counter management Peripheral control state counter management req_mem req_peri AHB slave interface AHB master interface AHB master ...

Page 317: ...xM0ADDR DMA_CHxM1ADDR DMA_CHxPADDR Memory to memory 10 DMA_CHxPADDR DMA_CHxM0ADDR DMA_CHxM1ADDR Note 1 The MBS bit in DMA_CHxCTL register determines whichis selected as the memory buffer address in DMA_CHxM0ADDR and DMA_CHxM1ADDR register For more information refer to sectionSwitch buffer mode 2 The TM bits in DMA_CHxCTL register are forbidden to configure to 0b11 or the channel will be automatica...

Page 318: ...s channel is forced to return 0 except for both the secure state and the privileged state of this channel x SECM and PRIV bits of the DMA_CHxSCTL register which are readable by a non secure software A non secure write access to a register field of this channel has no impact When a channel is configured in secure mode a secure software can separately configure as secure or non secure the AHB DMA ma...

Page 319: ...privileged access mode at a channel level When a channel x is configured in privileged mode the following access controls rules are applied Anunprivileged read accesstoaregisterfieldof this channel is forcedto return0 except for both the privileged state and the secure state of this channel x PRIV and SECM bits of the DMA_CHxSCTL register whichare readable by an unprivileged software An unprivileg...

Page 320: ...able 12 3 Peripheral requeststo DMA1 As listed in the Table 12 2 Peripheral requests to DMA0 and Table 12 3 Peripheral requests to DMA1 a peripheral request can be connected to two different DMA channels It is forbidden to simultaneously enable these two DMA channels with selecting the same peripheral request For example in DMA0 I2C0_RXis connected to channel 0 and channel 5 When the PERIEN bits i...

Page 321: ...6_ UP TIMER15_ CH0 TIMER15_ UP TIMER16_ CH0 TIMER16_ UP 110 TIMER0_TG TIMER0_C H0 TIMER0_CH 1 TIMER0_C H0 TIMER0_C H3 TIMER0_T G TIMER0_C MT TIMER0_U P TIMER0_C H2 111 HPDF_FL T0 HPDF_FLT1 12 4 3 Data process Arbitration Two arbiters are implemented in each DMA respectively for memory and peripheral port When two or more requests are received at the same time the arbiter determines which channel i...

Page 322: ...ansfer the remaining data items are transferred in single transaction AMBA protocol specifies that bursts must not cross a 1kB address boundary or a transfer error will be responsed to the master In each DMA the peripheral burst transfer crossing a 1kB address boundary is decomposed to 4 8 or 16 single transactions depend on the PBURST bits as the same as the memory burst transfer Transfer counter...

Page 323: ...ster The number of data bytes must be an integer multiple of the bytenumber of a peripheral burst transfer and a memory burst transfer to gurantee an integrated memory and peripheral burst transfer a CNT PBURST_beats must be an integer b CNT PWIDTH_bytes MBURST_beats MWIDTH_bytes must be an integer PWIDTH_bytes is the byte number of the peripheral transfer width 1 for 8 bit 2 for 16 bit and 4 for ...

Page 324: ...the FIFO counter critical value configured in the FCCV bits of the DMA_CHxFCTL register controls the memory data processing Only when the FIFO counter is reached the critical value the data in the FIFO are entirely poped and written into the memory address To gurantee a good DMA behavior the FIFO counter critical value FCCV bits in the DMA_CHxFCTL register must be an integer multiple of a memory b...

Page 325: ... DMA data access and the FIFO counter critical value configured in the FCCV bits of the DMA_CHxFCTL register has no meaning In single datamode DMA responds thesourcerequestonly whentheFIFOis empty pushing the data reading from the source address into the FIFOwhatever the source transfer width is When the FIFO is not empty DMA responds the destinationrequest poping the data from the FIFO and writin...

Page 326: ...B1 B0 word 4 word 3 word 2 word 1 PAIF 0 MWIDTH 8 bit PAIF 1 MWIDTH 16 bit PAIF 0 MWIDTH 32 bit Suppose the CNT bits are 8 the PWIDTH bits are equal to 01 and both PNAGA and MNAGA are set The DMA transfer operations for different MWIDTH are shown in the Figure 12 5 Data packing unpacking when PWIDTH 01 Figure 12 5 Data packing unpacking when PWIDTH 01 read 0xB1B0 15 0 0x0 read 0xB5B4 15 0 0x4 read...

Page 327: ...gorithm are implemented independently for memory and peripheral including the fixed mode and the increased mode The PNAGA and MNAGA bit in the DMA_CHxCTL register are used to configure the next address generation algorithm of peripheral and memory In the fixed mode the next address is always equal to the base address configured in the base address registers DMA_CHxPADDR DMA_CHxM0ADDR and DMA_CHxM1...

Page 328: ...mission thememorybuffernot beingprocessedby DMA canbeaccessedby otherAHB masters Inswitch buffermode thebaseaddress ofthememory buffer not accessedby DMA can be updated even if the channel is enabled The MBS bit in the DMA_CHxCTL register is configured to select which memory buffer is accessed by DMA at the first DMA transfer before the channel is enabled In switch buffer mode this bit switches au...

Page 329: ...er and writes data into the corresponding memory address In multi data mode when the FIFO counter reaches the critical value DMA starts single or burst memory transfers to entirely fetch the FIFO data and write to the memory Memory to peripheral mode In single data mode when the channel is enabled DMA starts a single memory transfer and pushes the reading data into the FIFO immediately During the ...

Page 330: ...al is the transfer flow controller the DMA transfer is completed when the last peripheral request has been responded and the contents of the FIFO have been entirely transferred into the memory Memory to peripheral mode If DMA is the transfer flow controller when the CNT bits in the DMA_CHxCNT register reach to zero an end of transfer is achieved If peripheral is the transfer flow controller the DM...

Page 331: ...us error When the memory or peripheral port attempts to access an address beyond the access scope a bus error is detected and the DMA transfer is stopped immediately without setting the FTFIFx If this error is aroused by the peripheral port the CNT bits are still decreased by 1 For more information about the bus error refer to section Error Register access error In switch buffer mode an access err...

Page 332: ...R corresponding with the MBS bit in the DMA_CHxCTL register 10 Configure the DMA_CHxCNT register to set the total transfer data number 11 Configure the CHEN bit with 1 in the DMA_CHxCTL register to enable the channel When restarting the suspended DMA transfer it is recommended to respect the following steps 1 Read the CHEN bit and ensure the DMA suspend operation has been completed When the CHEN b...

Page 333: ...ypes Flag Full transfer finish flag and half transfer finish flag Exception Single data mode exception and FIFO exception Error Transfer access error and FIFO error When the exception events occur the DMA transmission is not affected and continues transferring normally When the error events are detected the DMA transmission is stopped These three types of event are described in detail in the follo...

Page 334: ...o memory When a peripheral request is valid and the FIFO is not empty there are two or more data items stored in the FIFO after responding the peripheral request which could be a problem for the subsequent processing of the data When the single data mode exception is asserted and the enabled bit for the single data mode exception interrupt is set an interrupt is generated FIFO exception When a FIF...

Page 335: ...uffer is enabled If the software attempts to update a memory address register currently accessed by the DMA controller a register access error is detected For example when the memory 0 buffer is the current source or destination a write access on the DMA_CHxM0ADDR register could produce a register access error When a register access error occurs the DMA transmission is stopped when the current mem...

Page 336: ...ion of DMA0 and DMA1 DMA0 memory port peripheral port DMA config FMC_I FMC_D SRAM0 AHB1 QSPI AHB2 SRAM1 SRAM2 TCMSRAM ADDSRAM APB1 APB2 Bus matrix Peripheral request DMA1 memory port peripheral port DMA config FMC_I FMC_D SRAM0 AHB1 QSPI AHB2 SRAM1 SRAM2 CCMSRAM ADDSRAM APB1 APB2 Bus matrix Peripheral request ...

Page 337: ...dw are set and softw are cleared by configuring DMA_INTC0 register 0 Transfer has not finished on channel x 1 Transfer has finished on channel x 26 20 10 4 HTFIFx Half transfer finish flag of channel x x 0 3 Hardw are set and softw are cleared by configuring DMA_INTC0 register 0 Half number of transfer has not finished on channel x 1 Half number of transfer has finished on channel x 25 19 9 3 TAEI...

Page 338: ... x 1 Transfer has finished on channel x 26 20 10 4 HTFIFx Half transfer finish flag of channel x x 4 7 Hardw are set and softw are cleared by configuring DMA_INTC1 register 0 Half number of transfer has not finished on channel x 1 Half number of transfer has finished on channel x 25 19 9 3 TAEIFx Transfer access error flag of channel x x 4 7 Hardw are set and softw are cleared by configuring DMA_I...

Page 339: ...ag of channel x x 0 3 0 No effect 1 Clear half transfer finish flag 25 19 9 3 TAEIFCx Clear bit for ransfer access error flag of channel x x 0 3 0 No effect 1 Clear transfer access error flag 24 18 8 2 SDEIFCx Clear bit for single data mode exception of channel x x 0 3 0 No effect 1 Clear single data mode exception flag 23 17 7 1 Reserved Must be kept at reset value 22 16 6 0 FEEIFCx Clear bit for...

Page 340: ... single data mode exception flag 23 17 7 1 Reserved Must be kept at reset value 22 16 6 0 FEEIFCx Clear bit for FIFO error and exception of channel x x 4 7 0 No effect 1 Clear FIFO error and exception flag 12 6 5 Channel x control register DMA_CHxCTL x 0 7 where x is a channel number Address offset 0x10 0x18 x Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PERIEN ...

Page 341: ...R4 4 beat incrementing burst 10 INCR8 8 beat incrementing burst 11 INCR16 16 beat incrementing burst These bits can NOT be w ritten w hen CHEN is 1 These bits are automatically locked as 00 by hardw are immediately after enable CHEN if MDMEN in the DMA_CHxFCTL register is configured to 0 20 Reserved Must be kept at reset value 19 MBS Memory buffer select Hardw are and softw are set Hardw are and s...

Page 342: ...er w idth of memory Softw are set and clear 00 8 bit 01 16 bit 10 32 bit 11 Reserved These bits can NOT be w ritten w hen CHEN is 1 These bits are automatically locked as PWIDTH by hardw are immediately after enable CHEN if MDMEN in the DMA_CHxFCTL register is configured to 0 12 11 PWIDTH 1 0 Transfer w idth of peripheral Softw are set and clear 00 8 bit 01 16 bit 10 32 bit 11 Reserved These bits ...

Page 343: ...ed as the transfer flow controller 1 Peripheral is selected as the transfer flow controller This bit can NOT be w ritten w hen CHEN is 1 4 FTFIE Enable bit for full transfer finish interrupt Softw are set and clear 0 Disable full transfer finish interrupt 1 Enable full transfer finish interrupt 3 HTFIE Enable bit for half transfer finish interrupt Softw are set and clear 0 Disable half transfer fi...

Page 344: ... x 0 7 where x is a channel number Address offset 0x14 0x18 x Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CNT 15 0 Transfer counter These bits can NOT be w ritten w hen CHEN in the DMA_CHxCTL register is 1 These bits are related to PWIDTH D...

Page 345: ... a channel number Address offset 0x1C 0x18 x Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 M0ADDR 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M0ADDR 15 0 rw Bits Fields Descriptions 31 0 M0ADDR 31 0 Memory 0 base address When MBS in the DMA_CHxCTL register is read as to 0 these bits specific the memory base address accessed by DMA during the transmission These bits can...

Page 346: ...ad as 1 When memorty 1 is selected as memory tranfer area and MWIDTH in the DMA_CHxCTL register is 01 16 bit the LSB of these bits is ignored Access is automatically aligned to a half w ord address When memorty 1 is selected as memory tranfer area and MWIDTH in the DMA_CHxCTL register is 10 32 bit the tw o LSBs of these bits are ignored Access is automatically aligned to a w ord address 12 6 10 Ch...

Page 347: ...cked as 1 by hardw are immediately after enable CHEN in the DMA_CHxCTL register if TM in the DMA_CHxCTL register is configured to 10 1 0 FCCV 1 0 FIFO counter critical value Softw are set and clear 00 One w ord 01 Tw o Words 10 Three Words 11 Four Words These bits can NOT be w ritten w hen CHEN in the DMA_CHxCTL register is 1 When MDMEN is configured to 0 these bits has no meaning 12 6 11 Security...

Page 348: ...e corresponding bit in the DMA_SSCR register 0 No illegal access event on channel x 1 An illegal access event occurred on channel x 12 6 12 Security status clear register DMA_SSC Address offset 0x104 Reset value 0x0000 0000 This register may mix secure and non secure information depending on the secure modeof each channel SECM bit of the DMA_CHxSCTL register A secure software is able to set any fl...

Page 349: ...lds in this register is force to 0x0 by hardware Modifying the SECM bit must be performed by a secure write access to this register When the PRIV bit is set a secure and priviledged transfer is needed Modifying the PRIV bit must be performed by a privileged write access to this register When the SECM bit is set a secure and priviledged transfer is needed Setting any of the DSEC or SSEC bits must b...

Page 350: ...d CHEN 1 It is read only w hen the channel is enabled CHEN 1 1 SSEC Security of the DMA transfer from the source This bit can only be accessed read set or cleared by a secure softw are It must be a privileged softw are if the channel is in privileged mode This bit is cleared by hardw are w hen the securely w ritten data bit 0 is cleared on a secure reconfiguration of the channel as non secure A no...

Page 351: ...cessedby a debug tool via Serial Wire SW Debug Port or JTAG interface JTAG Debug Port 13 2 1 Switch JTAG or SW interface By default the JTAG interface is active The sequence for switching from JTAG to SWD is Send 50 or more TCK cycles withTMS 1 Send the 16 bit sequence on TMS 1110011110011110 0xE79E LSB first Send 50 or more TCK cycles withTMS 1 The sequence for switching from SWD to JTAG is Send ...

Page 352: ...IDCODE is 0x790007A3 13 2 4 Debug reset The JTAG DP and SW DP register are in the power on reset domain The System reset initializes the majority of the Cortex M33 excluding NVIC and debug logic FPB DWT and ITM The NJTRST reset canreset JTAGTAP controlleronly So it canperform debugfeature under system reset Such as halt after reset which is the debugger sets halt under system reset and the core ha...

Page 353: ...bug in sleep mode 13 3 2 Debug support for TIMER I2C WWDGT FWDGT and RTC When the core halted and the corresponding bit in DBG control register 1 2 DBG_CTL1 2 is set the following behaved For TIMER the timer counters stopped and hold for debug For I2C SMBUS timeout hold for debug For WWDGT or FWDGT the counter clock stopped for debug For RTC the counter is stopped for debugging ...

Page 354: ...tant 13 4 2 Control register 0 DBG_CTL0 Address offset 0x04 Reset value 0x0000 0000 power reset only This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRACE _MODE TRACE _IOEN Reserved STB_ HOLD DSLP_ HOLD SLP_ HOLD rw rw rw rw rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7...

Page 355: ...no effect 1 At the Deep sleep mode the clock of AHB bus and system clock are provided by CK_IRC16M 0 SLP_HOLD Sleep mode hold register This bit is set and reset by softw are 0 no effect 1 At the sleep mode the clock of AHB is on 13 4 3 Control register 1 DBG_CTL1 Address offset 0x08 Reset value 0x0000 0000 power reset only This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 ...

Page 356: ...s bit is set and reset by softw are 0 no effect 1 hold the RTC counter for debugging w hen the core is halted 9 5 Reserved Must be kept at reset value 4 TIMER5_HOLD TIMER5 hold bit This bit is set and reset by softw are 0 no effect 1 hold the TIMER5 counter for debugging w hen the core is halted 3 TIMER4_HOLD TIMER4 hold bit This bit is set and reset by softw are 0 no effect 1 hold the TIMER4 coun...

Page 357: ...3 2 1 0 Reserved TIMER0_ HOLD rw Bits Fields Descriptions 31 25 Reserved Must be kept at reset value 24 TIMER16_HOLD TIMER16 hold bit This bit is set and reset by softw are 0 no effect 1 hold the TIMER16 counter for debugging w hen the core is halted 23 TIMER15_HOLD TIMER15 hold bit This bit is set and reset by softw are 0 no effect 1 hold the TIMER15 counter for debugging w hen the core is halted...

Page 358: ... related computational burden from the MCU 14 2 Characteristics High performance 2 5MSPs for 12 bit resolution Programmable samplingtime Data alignment with built in data registers DMA support for regular channels and inserted channels Analog input channels 9 external analog inputs 1 channel for internal temperature sensor VSENSE 1 channel for internal reference voltage VREFINT 1 channel for exter...

Page 359: ... givetheADCinternal signals andpins description Table 14 1 ADC internal signals Internal signal name Signal type Description VSENSE Input Internal temperature sensor output voltage VREFINT Input Internal voltage reference output voltage Table 14 2 ADC pinsdefinition Name Signal type Remarks VDDA Input analog pow er supply Analog pow er supply equals to VDD and 2 5V VDDA 3 6V VSSA Input analog pow ...

Page 360: ...0 OVSE TOVS Over sampler VREFINT RVOF DMA request 14 4 1 ADC clock The ADCCLK clock provided by the clock controller is synchronous with the AHB and APB2 clock Themaximumfrequency is 35MHz TheRCUcontrollerhas adedicatedprogrammable prescaler for the ADC clock 14 4 2 ADCON switch The ADC module is enabled or disabled by configuring the ADCON bit in the ADC_CTL1 register The ADC module will keep in ...

Page 361: ...ernal trigger is active Figure 14 2 Single conversion mode CH2 CH2 CH2 CH2 CH2 EOC Regular trigger Sample Convert After conversion of a single regular channel the conversion data will be stored in the ADC_RDATA register the EOC will be set An interrupt will be generated if the EOCIE bit is set After conversion of a single injected channel the conversion data will be stored in the ADC_IDATA0 regist...

Page 362: ...Convert CH2 Software procedure for continuous conversion on a regular channel 1 Set the CTN bit in the ADC_CTL1 register 2 Configure RSQ0 with the analog channel number 3 Configure ADC_SAMPTx register 4 Configure ETMRC and ETSRC bits in the ADC_CTL1 register if it is needed 5 Set the SWRCST bit or generate an external trigger for the regular group 6 Wait for the EOC flag to be set 7 Read the conve...

Page 363: ...erted trigger EOC One circle of regular group RL 8 CH9 CH10 CH8 CH6 CH9 CH10 EOIC One circle of inserted group IL 4 Regular trigger Sample Convert CH4 CH0 Software procedure for scan conversion on a regular channel group 1 Set theSM bit intheADC_CTL0registerandtheDMA bit intheADC_CTL1 register 2 Configure ADC_RSQx and ADC_SAMPTx registers 3 Configure the ETMRC and ETSRC bits in the ADC_CTL1 regist...

Page 364: ...continuous conversion mode will be enabled when the DISIC bit in the ADC_CTL0 register is set In this mode the ADC performs one conversion which is a part of the sequence of conversions selected in the ADC_ISQ register When the corresponding software trigger or external trigger is active the ADC samples and coverts the next channel selected in the ADC_ISQregister until all the channels in the inse...

Page 365: ...riting 0 14 4 5 Inserted channel management Auto insertion The inserted group channels are automatically converted after the regular group channels when the ICA bit in ADC_CTL0 register is set In this mode the external trigger on inserted channels cannot be enabled A sequence of up to 13 conversions programmed in the ADC_RSQ0 ADC_RSQ2 and ADC_ISQ registers can be used to convert in this mode In ad...

Page 366: ...LT registers are used to specify the high and low threshold The comparison is done before the alignment so the threshold value is independent of the alignment whichis specifiedby theDALbit intheADC_CTL1register Oneormorechannels which are selected by the RWDEN IWDEN WDSC and WDCHSEL 4 0 bits inADC_CTL0 register can be monitored by the analog watchdog 14 4 7 Data alignment The alignment of data sto...

Page 367: ...es the total conversion time is 1 5 12 5 ADCCLK cycles that means 0 4us 14 4 9 External trigger The conversion of regular or inserted group can be triggered by rising falling edge of external trigger inputs The ETMRC 1 0 and ETMIC 1 0 bits in the ADC_CTL1 register control the trigger modes of regular and inserted group respectively The external trigger source of regular channel group is controlled...

Page 368: ...1101 Reserved 1110 Reserved 1111 EXTI_11 External signal Table 14 5 External trigger for inserted channelsof ADC ETSIC 3 0 Trigger source Trigger type 0000 TIMER0_CH3 Internal on chip signal 0001 TIMER0_TRGO 0010 TIMER1_CH0 0011 TIMER1_TRGO 0100 TIMER2_CH1 0101 TIMER2_CH3 0110 TIMER3_CH0 0111 TIMER3_CH1 1000 TIMER3_CH2 1001 TIMER3_TRGO 1010 TIMER4_CH3 1011 TIMER4_TRGO 1100 Reserved 1101 Reserved 1...

Page 369: ...edure for recovering the ADC from ROVF state 1 Clear DMA bit of ADC_CTL1 to 0 2 Clear ADCON bit of ADC_CTL1 to 0 3 Clear CHEN bit of DMA_CHxCTL to 0 with reinit DMA module 4 Clear ROVF bit of ADC_STAT to 0 5 Set CHEN bit of DMA_CHxCTL to 1 6 Set DMA bit of ADC_CTL1 to 1 7 Set ADCON bit of ADC_CTL1 to 1 8 Wait T setup 9 Start conversion with software or trigger 14 4 12 Temperature sensor internal r...

Page 370: ...lease refer to device datasheet for more information Avg_Slope Average Slope for curve between Temperature vs Vtemperature the typical value please refer to device datasheet 14 4 13 On chip hardware oversampling The on chip hardwareoversampling unit which is enabled by OVSEN bit in the ADC_OVSAMPCTL register provides higher data resolution at the cost of lower output data rate It provides a result...

Page 371: ...earest Table 14 6 Maximum output results for N and M combimations grayed values indicatestruncation belowgives thedataformat for thevarious N andM combinations and the raw conversion data equals 0xFFF Table 14 6 Maximum output results for N and M combimations grayed values indicatestruncation Oversa mpling ratio Max Raw data No shift OVSS 0000 1 bit shift OVSS 0001 2 bit shift OVSS 0010 3 bit shif...

Page 372: ...80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF When compared to standard conversion mode the conversion timings of oversampling mode do not change and the sampling time is maintained the same as that of standard conversion mode during the whole oversampling sequence New data are provided every N conversion with an equivalent delay equal to N x tADC N x tSMPL tCONV 14 2 14 4 14 ADC interrupts ...

Page 373: ...bit is set by hardw are w hen the regular data registers are overflow in single mode or multi mode This flag is only set w hen DMA is enabled or end of conversion mode is set to 1 EOCM 1 The recent regular data is lost w hen this bit is set Cleared by softw are writing 0 to it 4 STRC Start flag of regular channel group 0 No regular channel group started 1 Regular channel group started Set by hardw...

Page 374: ...ntrol register 0 ADC_CTL0 Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved ROVFIE Reserved RWDEN IWDEN Reserved rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DISNUM 2 0 DISIC DISRC ICA WDSC SM EOICIE WDEIE EOCIE WDCHSEL 4 0 rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 27 Reserved Must ...

Page 375: ...sable 1 Inserted channel group convert automatically enable 9 WDSC When in scan mode analog w atchdog is effective on a single channel 0 Analog w atchdog is effective on all channels 1 Analog w atchdog is effective on a single channel 8 SM Scan mode 0 Scan mode disable 1 Scan mode enable 7 EOICIE Interrupt enable for EOIC 0 EOIC interrupt disable 1 EOIC interrupt enable 6 WDEIE Interrupt enable fo...

Page 376: ... 31 Reserved Must be kept at reset value 30 SWRCST Softw are start on regular channel Setting 1 on this bit starts a conversion of a group of regular channels It is set by softw are and cleared by softw are or by hardw are after the conversion starts 29 28 ETMRC 1 0 External trigger mode for regular channel 00 External trigger for regular channel disable 01 Rising edge of external trigger for regu...

Page 377: ...l enable 11 Rising and falling edge of external trigger for inserted channel enable 19 16 ETSIC 3 0 External trigger select for inserted channel 0000 TIMER0 CH3 0001 TIMER0 TRGO 0010 TIMER1 CH0 0011 TIMER1 TRGO 0100 TIMER2 CH1 0101 TIMER2 CH3 0110 TIMER3 CH0 0111 TIMER3 CH1 1000 TIMER3 CH2 1001 TIMER3 TRGO 1010 TIMER4 CH3 1011 TIMER4 TRGO 1100 Reserved 1101 Reserved 1110 Reserved 1111 EXTI line 15...

Page 378: ...enable 0 ADCON ADC ON The ADC w ill be w aked up w hen this bit is changed from low to high and take a stabilization time 0 ADC disable and pow er dow n 1 ADC enable 14 5 4 Sample time register 0 ADC_SAMPT0 Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserv...

Page 379: ...w Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 27 SPT9 2 0 Refer to SPT0 2 0 description 26 24 SPT8 2 0 Refer to SPT0 2 0 description 23 21 SPT7 2 0 Refer to SPT0 2 0 description 20 18 SPT6 2 0 Refer to SPT0 2 0 description 17 15 SPT5 2 0 Refer to SPT0 2 0 description 14 12 SPT4 2 0 Refer to SPT0 2 0 description 11 9 SPT3 2 0 Refer to SPT0 2 0 description 8 6 SPT2 2 0 Ref...

Page 380: ...l be subtracted from the raw converted data w hen converting inserted channels The conversion result can be read from the ADC_IDATAx registers 14 5 7 Watchdog high threshold register ADC_WDHT Address offset 0x24 Reset value 0x0000 0FFF This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WDHT 11 0 rw...

Page 381: ...Regular sequence register 0 ADC_RSQ0 Address offset 0x2C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RL 3 0 Reserved rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 20 RL 3 0 Regular channel group length The total number of conversion in regular group...

Page 382: ...00 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RSQ5 4 0 RSQ4 4 0 RSQ3 4 1 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSQ3 0 RSQ2 4 0 RSQ1 4 0 RSQ0 4 0 rw rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 25 RSQ5 4 0 Refer to RSQ0 4 0 description 24 20 RSQ4 4 0 Refer to RSQ0 4 0 description 19 15 RSQ3 4 0...

Page 383: ...to ISQ0 4 0 description 14 10 ISQ2 4 0 Refer to ISQ0 4 0 description 9 5 ISQ1 4 0 Refer to ISQ0 4 0 description 4 0 ISQ0 4 0 The channel number 0 11 is w ritten to these bits to select a channel as the nth conversion in the inserted channel group Different from the regular conversion sequence the inserted channels are converted starting from 4 IL 1 0 1 if IL 1 0 length is less than 4 IL Insert cha...

Page 384: ...2 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDATA 15 0 r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 RDATA 15 0 Regular channel data These bits contain the conversion result from regular channel w hich is read only 14 5 15 Oversampling control register ADC_OVSAMPCTL Address offset 0x80 Reset value 0x0000 0000 This register has to be accessed by w...

Page 385: ...0010 Shift 2 bits 0011 Shift 3 bits 0100 Shift 4 bits 0101 Shift 5 bits 0110 Shift 6 bits 0111 Shift 7 bits 1000 Shift 8 bits Other reserved Note Softw are is allow ed to w rite this bit only w hen ADCON 0 w hich ensures that no conversion is ongoing 4 2 OVSR 2 0 Oversampling ratio This bit filed defines the number of oversampling ratio 000 2x 001 4x 010 8x 011 16x 100 32x 101 64x 110 128x 111 256...

Page 386: ...d Must be kept at reset value 23 TSVREN Channel 9 temperature sensor and 10 internal reference voltage enable of ADC 0 Channel 9 and 10 of ADC disable 1 Channel 9 and 10 of ADC enable 22 VBATEN Channel 11 1 4 voltageof external battery enable of ADC 0 Channel 11 of ADC disable 1 Channel 11 of ADC enable 21 19 Reserved Must be kept at reset value 18 16 ADCCK 2 0 ADC clock These bits configure the A...

Page 387: ...Thereupon the FWDGT can operate even if the main clock fails It s suitable for the situation that requires an independent environment and lower timing accuracy The free watchdog timer causes a reset when the internal down counter reaches 0 The register write protection function in free watchdog timer can be enabled to prevent it from changing the configuration unexpectedly 15 1 2 Characteristics F...

Page 388: ...d reload the counter before the counter reaches 0x000 The FWDGT_PSC register and the FWDGT_RLD register are write protected Before writing these registers the software should write the value 0x5555 to the FWDGT_CTL register These registers will beprotectedagainby writingany othervaluetothe FWDGT_CTLregister When an update operation of the prescaler register FWDGT_PSC or the reload value register F...

Page 389: ...GD32W51x User Manual 389 The FWDGT timeout can be more accurate by calibrating the IRC32K ...

Page 390: ...fferent fuctions are realized by w riting these bits w ith different values 0x5555 Disable the FWDGT_PSC and FWDGT_RLD w rite protection 0xCCCC Start the free w atchdog timer counter When the counter reduces to 0 the free w atchdog timer generates a reset 0xAAAA Reload the counter Prescaler register FWDGT_PSC Address offset 0x04 Reset value 0x0000 0000 This register can be accessed by half word 16...

Page 391: ... 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RLD 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 RLD 11 0 Free w atchdog timer counter reload value Write 0xAAAA in the FWDGT_ CTL register w illreload the FWDGT counter w ith the RLD value These bits are w rite protected Write 0x5555 in the FWDGT_CTL register before w riti...

Page 392: ...atchdog timer counter reload value update During a w rite operation to FWDGT_RLD register this bit is set and the value read from FWDGT_RLD register is invalid This bit is reset by hardw are after the update operation of FWDGT_RLD register 0 PUD Free w atchdog timer prescaler value update During a w rite operation to FWDGT_PSC register this bit is set and the value read from FWDGT_PSC register is ...

Page 393: ...dog timer clock is prescaled from the APB1 clock The window watchdog timer is suitable for the situation that requires an accurate timing 15 2 2 Characteristics Programmable free running 7 bit down counter Generate reset in two conditions when WWDGT is enabled Reset when the counter reached 0x3F The counter is refreshed when the value of the counter is greater than the window register value Early ...

Page 394: ...ter WWDGT_CFG specifies the window value The software can prevent the reset event by reloading the down counter The counter value is less than the window value and greater than 0x3F otherwise the watchdog causes a reset The early wakeup interrupt EWI is enabled by setting the EWIE bit in the WWDGT_CFG register and the interrupt will be generated when the counter reaches 0x40 or the counter is refr...

Page 395: ...clock period measured in ms The table below shows the minimum and maximum values of the tWWDGT Table 15 2 Min max timeout value at 45 MHz fPCLK1 Prescaler divider PSC 1 0 Min timeout value CNT 6 0 0x40 Max timeout value CNT 6 0 0x7F 1 1 00 91 02 μs 5 83 ms 1 2 01 182 04 μs 11 65 ms 1 4 10 364 08 μs 23 30 ms 1 8 11 728 18 μs 46 60 ms If the WWDGT_HOLD bit in DBG module is cleared the WWDGT continue...

Page 396: ...og timer Cleared by a hardw are reset Writing 0 has no effect 0 Window w atchdog timer disabled 1 Window w atchdog timer enabled 6 0 CNT 6 0 The value of the w atchdog timer counter A reset occur w hen the value of this counter decreases from 0x40 to 0x3F When the value of this counter is greater than the w indow value w riting this counter also causes a reset Configuration register WWDGT_CFG Addr...

Page 397: ...ritten w hen the value of the w atchdog counter is greater than the Window value Status register WWDGT_STAT Address offset 0x08 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EWIF rc_w0 Bits Fields Descriptions 31 1 Reserved Must be kept at reset value 0...

Page 398: ... adjustment by shift function Time stamp function for saving event time Two Tamper sources can be chosen and tamper type is configurable Programmable calendar and two field maskable alarms Maskable interrupt source Alarm 0 andAlarm 1 Time stamp detection Tamper detection Auto wakeup event Twenty 32 bit 80 bytes total universal backup registers which can keep data under power saving mode Backup reg...

Page 399: ... Auto reload wakeup timer WTCS RTC 2 4 8 16 ck_spre Default 1 Hz RTC Clock RTC_ALARM WTF The RTC unit includes Alarm event interrupt Tamper event interrupt 32 bit backup registers Optional RTC output function 512Hz default prescale PC15 PA3 PA8 1Hz default prescale PC15 PA3 PA8 Alarm event polarity is configurable PC15 PA3 PA8 Automatic wakeup event polarity is configurable PC15 PA3 PA8 Optional R...

Page 400: ...SHAD control bit decides the location when APB bus accesses the RTC calendar register RTC_DATE RTC_TIME and RTC_SS By default the BPSHAD is cleared and APB bus accessestheshadowcalendarregisters Shadow calendarregistersis updatedwiththevalue of real calendar registers every two RTC clock and at the same time RSYNF bit will be set once This update mechanism is not performed in Deep Sleep mode and S...

Page 401: ...thedown counter is running When it reaches 0 the WTF flag is set and the wakeup counter is automatically reloaded with RTC_WUT value When WTF asserts software must then clear it If WTIE is set and this counter reaches 0 a wakeup interrupt will make system exit from the power saving mode System reset has no influence on this function 16 3 6 RTC initialization and configuration RTC register write pr...

Page 402: ...theasynchronousandsynchronousprescalerfactors inRTC_PSCregister 3 Write the initial calendar values into the shadow calendar registers RTC_TIME and RTC_DATE and use the CS bit in the RTC_CTL register to configure the time format 12 or 24 hours 4 Exit the initialization mode by setting INITM 0 About 4 RTC clock cycles later real calendar registers will load from shadow registers and calendar counte...

Page 403: ... and at this time point the shadow registers will be updated to current time and date To ensure consistency of the 3 values RTC_SS RTC_TIME and RTC_DATE below consistency mechanism is used in hardware 1 Reading RTC_SS will lock the updating of RTC_TIME and RTC_DATE 2 Reading RTC_TIME will lock the updating of RTC_DATE 3 Reading RTC_DATE will unlock updating of RTC_TIME and RTC_DATE If thesoftwarew...

Page 404: ...system reset is valid the bits or registers mentioned before are reset to the default value Backup domain reset will affect the following registers and system reset will not affect them RTC current real time calendar registers RTC Control register RTC_CTL RTC Prescaler register RTC_PSC RTC Wakeup timer register RTC_WUT RTC Coarse calibration register RTC_COSC RTC High resolution frequency compensa...

Page 405: ... compared to the nearest RTC_REFIN clock edge In most cases the two clock edges are aligned every time But when two clock edges are misaligned for the reason of LXTAL poor precision the RTC reference clock detection function will shift the 1Hz clock edge a little to make next 1Hz clock edge aligned to reference clock edge When REFEN 1 a time window is applied at every second update time different ...

Page 406: ...it The full calibration window lasts 64 minutes The first 2xCOSS minutes of this 64 minute window are take adjust About 2PPM resolution is taken for negative calibration and about 4PPM resolution is taken for positive calibration Note The calibration can be performed either on LXTAL or HXTAL clock If FACTOR_A 6 the calibration may not work correctly Example FACTOR_A and FACTOR_S are default values...

Page 407: ...anadjust theRTCcycles from 511to 512cycles in the period time which means the calibration range is 487 1PPM to 488 5PPM with a resolution of about 0 954PPM When calibration function is running the output frequency of calibration is calculated by the following formula 𝑓cal 𝑓rtcclk 1 𝐹𝑅𝐸𝑄𝐼 512 𝐶𝑀𝑆𝐾 2𝑁 𝐶𝑀𝑆𝐾 𝐹𝑅𝐸𝑄𝐼 512 17 3 Note N 20 19 18 for 32 16 8 seconds window period Calibration when FACTOR_A 3 W...

Page 408: ... Using exactly 8s periodto measure the accuracy of the calibration 1Hz output can guarantee the measure is within 1 907PPM 0 5 RTCCLK cycles over 8s Re calibration on the fly When the INITF bit is 0 software can update the value of RTC_HRFC using following steps 1 Wait the SCPF 0 2 Write the new value into RTC_HRFC register 3 After 3 ck_apre clocks the new calibration settings take effect 16 3 13 ...

Page 409: ...sters and the device secrets erased by tamp_erase signal can be reset by software by setting the BKERASE bit in the RTC_TAMP register Timestamp on tamper event The TPTS bit can control whether the tamper detection function is used as time stamp function If the bit is set to 1 the TSF bit will be set when the tamper event detected as if enable thetime stampfunction WhatevertheTPTS bit is theTPxF wi...

Page 410: ...When the COS bit is set to 0 this is default and asynchronous prescaler is set to 0x7F FACTOR_A the frequency of RTC_CALIB is frtcclk 64 When the RTCCLK is 32 768KHz RTC_CALIB output is corresponding to 512Hz It s recommend to using rising edge of RTC_CALIB output for there may be a light jitter on falling edge When the COS bit is set to 1 the RTC_CALIB frequency is 𝑓𝑟𝑡𝑐_𝑐𝑎𝑙𝑖𝑏 𝑓𝑟𝑡𝑐𝑐𝑙𝑘 𝐹𝐴𝐶𝑇𝑂𝑅_𝐴 1 𝐹...

Page 411: ...ure mode Read in secure mode Read in non secure mode INITSECP 0 Allow ed access RTC_TIME RTC_DATE and TC_PSC register INITM in RTC_ICSR CR in RTC_CTL INITSECP in RTC_SPM_CTL Allow ed access RTC_TIME RTC_DATE and TC_PSC register INITM in RTC_ICSR CR control bits in RTC_CTL INITSECP in RTC_SPM_CTL Allow ed access RTC_TIME RTC_DATE and TC_PSC register INITM in RTC_ICSR CR control bits in RTC_CTL INIT...

Page 412: ... RTC_STATC ALRM1F in RTC_STAT ALRM1MSF in RTC_SMI_STAT WUTSECP 0 Allow ed access RTC_WUT register WTEN WTIE and WTCS control bits in the RTC_CTL WTFC in the RTC_STATC WTF in RTC_STAT WTSMF in RTC_SMI_STAT WUTSECP in the RTC_SPM_CTL Allow ed access RTC_WUT register WTEN WTIE and WTCS control bits in the RTC_CTL WTFC in the RTC_STATC WTF in RTC_STAT WTSMF in RTC_SMI_STAT TSSECP 0 Allow ed access RTC...

Page 413: ...TZIAC will generate a message of flag or interrupt When only few bits of the register are protected TZIAC will not generate any messages except backup registers protection Afterthe systemis reset theRTCprotectionrelatedconfigurationunchanged Aslongas one of the functions oftheRTC is configuredto besecured thereset andclock control ofthe RTC are also secure in the RCU 16 3 18 RTC privilege protecti...

Page 414: ...ess RTC_SHIFTCTL and RTC_COSC registers A1H S1H and REFEN control bits in the RTC_CTL CALPRIP in the RTC_PPM_CTL Allow ed access RTC_SHIFTCTL and RTC_COSC registers A1H S1H and REFEN control bits in the RTC_CTL CALPRIP in the RTC_PPM_CTL Allow ed access RTC_SHIFTCTL and RTC_COSC registers A1H S1H and REFEN control bits in the RTC_CTL CALPRIP in the RTC_PPM_CTL ALRM0PRIP 1 Allow ed access RTC_ALRM0...

Page 415: ...trol bits in RTC_CTL WTFC in RTC_STATC WTF in RTC_STAT WTNSMF in RTC_NSMI_STAT WTSMF in RTC_SMI_STAT TSPRIP 1 Allow ed access RTC_TTS RTC_DTS and RTC_SSTS registers TSEN TSIE TSEG control bits in RTC_CTL TSOVRFC and TSFC bits in RTC_STATC TSF TSOVRF in RTC_STAT TSSMF TSOVRSMF in RTC_SMI_STAT TSPRIP in RTC_PPM_CTL Allow ed access RTC_TTS RTC_DTS and RTC_SSTS registers TSEN TSIE TSEG control bits in...

Page 416: ...n status of the backup domain register is configured through bits BKPRWSECP 7 0 and BKPWSECP 7 0 in RTC_SPM_CTL register Configure protection zone A through BKPRWSECP 7 0 and BKPRWPRIP configure protection zone B through BKPRWSECP 7 0 BKPWSECP 7 0 and BKPWPRIP The backup domain registers security protection configuration is shown in Figure 16 2 Backup registers secure protections configuration Fig...

Page 417: ...e Below steps should be followed if you want to use the RTC alarm tamper timestamp auto wakeup interrupt 1 Configure and enable the corresponding interrupt line to RTC alarm tamper timest amp auto wakeup event of EXTI and set the rising edge for triggering 2 Configure and enable the RTC alarm tamper timestamp auto wakeup interrupt 3 Configure and enable the RTC alarm tamper timestamp auto wakeup f...

Page 418: ...lag Exit sleep Exit deep sleep and standby Alarm 0 ALRM0F ALRM0IE and ALRM0SECP 0 and RTCSECP 0 w rite 1 in ALRM0FC Y Y Alarm 1 ALRM1F ALRM1IE and ALRM0SECP 0 and RTCSECP 0 w rite 1 in ALRM0FC Y Y Wakeup WTF WTIE and WUTSECP 0 and RTCSECP 0 w rite 1 in WTFC Y Y Timestamp TSF TSIE and TSSECP 0 and RTCSECP 0 w rite 1 in TSFC Y Y Tamper 0 TP0F TPIE and TAMPSECP 0 and RTCSECP 0 Write 1 in TP0FC Y Y NO...

Page 419: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PM HRT 1 0 HRU 3 0 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MNT 2 0 MNU 3 0 Reserved SCT 2 0 SCU 3 0 rw rw rw rw Bits Fields Descriptions 31 23 Reserved Must be kept at reset value 22 PM AM PM mark 0 AM or 24 hour format 1 PM 21 20 HRT 1 0 Hour tens in BCD code 19 16 HRU 3 0 Hour units in BCD code 15 Reserved Must be kept at reset ...

Page 420: ...s of the w eek 0x0 Reserved 0x1 Monday 0x7 Sunday 12 MONT Month tens in BCD code 11 8 MONU 3 0 Month units in BCD code 7 6 Reserved Must be kept at reset value 5 4 DAYT 1 0 Day tens in BCD code 3 0 DAYU 3 0 Day units in BCD code 16 4 3 Control register RTC_CTL Address offset 0x08 System reset not affected Backup domain reset value 0x0000 0000 This register is writing protected the register can be ...

Page 421: ...RTC_ALARM 0 Disable invert output RTC_ALARM 1 Enable invert output RTC_ALARM 19 COS Calibration output selection Valid only w hen COEN 1 and prescalers are at default values 0 Calibration output is 512 Hz 1 Calibration output is 1Hz 18 DSM Daylight saving mark This bit is flexible used by softw are Often can be used to recording the daylight saving hour adjustment 17 S1H Subtract 1 hour w inter ti...

Page 422: ... Enable alarm function 8 ALRM0EN Alarm 0 function enable 0 Disable alarm function 1 Enable alarm function 7 CCEN Coarse calibration function enable 0 Disable function 1 Enable function Note FACTOR_A must be greater than 6 before enabled and can only be w ritten in initialization state 6 CS Clock System 0 24 hour format 1 12 hour format Note Can only be w ritten in initialization state 5 BPSHAD Sha...

Page 423: ...r can be protected globally or individually per bit can be configured to prevent non secure access or non privileged access This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SCPF r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INITM INITF RSYNF YCM SOPF WTWF ALRM1W F ALRM0W F rw r rc_w0 r r r r r Bits Fields Descriptions 31 17 Reserved Must b...

Page 424: ...nding 1 Shift function operation is pending 2 WTWF Wakeup timer w rite enable flag 0 Wakeup timer update is not allow ed 1 Wakeup timer update is allow ed 1 ALRM1WF Alarm 1 configuration can be w rite flag Set by hardw are if alarm register can be w rote after ALRM1EN bit has reset 0 Alarm registers programming is not allow ed 1 Alarm registers programming is allow ed 0 ALRM0WF Alarm 0 configurati...

Page 425: ...revent non secure access or non privileged access This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WTRV 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 WTRV 15 0 Auto w akeup timer reloads value Every WTRV 15 0 1 ck_w ut period the WTF bit is set after WTEN 1 The ck_w ut i...

Page 426: ...rse Calibration step When COSD 0 0x00 0 PPM 0x01 4 PPM approximate value 0x02 8 PPM approximate value 0x1F 126 PPM approximate value When COSD 1 0x00 0 PPM 0x01 2 PPM approximate value 0x02 4 PPM approximate value 0x1F 63 PPM approximate value 16 4 8 Alarm 0 time and date register RTC_ALRM0TD Address offset 0x1C System reset not effect Backup domain reset value 0x0000 0000 This registe can only be...

Page 427: ...sk hour field 1 Mask hour field 22 PM AM PM flag 0 AM or 24 hour format 1 PM 21 20 HRT 1 0 Hour tens in BCD code 19 16 HRU 3 0 Hour units in BCD code 15 MSKM Alarm minutes mask bit 0 Not mask minutes field 1 Mask minutes field 14 12 MNT 2 0 Minutes tens in BCD code 11 8 MNU 3 0 Minutes units in BCD code 7 MSKS Alarm second mask bit 0 Not mask second field 1 Mask second field 6 4 SCT 2 0 Second ten...

Page 428: ... Day of the w eek selected 0 DAYU 3 0 indicates the date units 1 DAYU 3 0 indicates the w eekday and DAYT 3 0 has no means 29 28 DAYT 1 0 Day tens in BCD code 27 24 DAYU 3 0 Day units or w eek day in BCD code 23 MSKH Alarm hour mask bit 0 Not mask hour field 1 Mask hour field 22 PM AM PM flag 0 AM or 24 hour format 1 PM 21 20 HRT 1 0 Hour tens in BCD code 19 16 HRU 3 0 Hour units in BCD code 15 MS...

Page 429: ... 0x0000 0000 when BPSHAD 0 Not affected when BPSHAD 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSC 15 0 r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 SSC 15 0 Sub second value This value is the counter value of synchronous prescaler Second fraction value is calculated ...

Page 430: ... ill delay because the synchronous prescaler is a dow n counter Delay seconds SFS FACTOR_S 1 When jointly using A1S and SFS the clock w ill advance Advance seconds 1 SFS FACTOR_S 1 Note Writing to this register w ill cause RSYNF bit to be cleared 16 4 13 Time of time stamp register RTC_TTS Address offset 0x30 Backup domain reset value 0x0000 0000 System reset no effect This register will record th...

Page 431: ...o effect This register will record the calendar date when TSF is set to 1 This register can be write protected to prevent non secure access or non privileged access Reset TSF bit will also clear this register This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DOW 2 0 MONT MONU 3 0 Reserved DAYT 1 0 DAYU 3 0...

Page 432: ... value This value is the counter value of synchronous prescaler w hen TSF is set to 1 16 4 16 High resolution frequency compensation register RTC_HRFC Address offset 0x3C Backup domain reset 0x0000 0000 System Reset no effect This register is write protected This register can be write protected to prevent non secure access or non privileged access This register has to be accessed by word 32 bit 31...

Page 433: ...ress offset 0x40 Backup domain reset 0x0000 0000 System reset no effect This register can be write protected to prevent non secure access or non privileged access This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BKERAS E Reserved TP1NOER TP0NOER AOT Reserved rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DISPU PRCH 1 0 FLT 1 0 FREQ 2 0 TPTS Reserve...

Page 434: ...secutive valid level samples w ill make an effective tamper event 0x2 Detecting tamper event using level mode 4 consecutive valid level samples w ill make an effective tamper event 0x3 Detecting tamper event using level mode 8 consecutive valid level samples w ill make an effective tamper event 10 8 FREQ 2 0 Sampling frequency of tamper event detection 0x0 Sample once every 32768 RTCCLK 1Hz if RTC...

Page 435: ...ge triggers a tamper detection event If tamper detection is in level mode FLT 0 0 Low level triggers a tamper detection event 1 High level triggers a tamper detection event 0 TP0EN Tamper 0 detection enable 0 Disable tamper 0 detection function 1 Enable tamper 0 detection function Note It s strongly recommended that reset the TPxEN before change the tamper configuration 16 4 18 Alarm 0 sub second ...

Page 436: ... ignored 0xC SSC 11 0 is to be compared and all others are ignored 0xD SSC 12 0 is to be compared and all others are ignored 0xE SSC 13 0 is to be compared and all others are ignored 0xF SSC 14 0 is to be compared and all others are ignored Note The bit 15 of synchronous counter SSC 15 in RTC_SS is never compared 23 15 Reserved Must be kept at reset value 14 0 SSC 14 0 Alarm sub second value This ...

Page 437: ...0 is to be compared and all others are ignored 0xD SSC 12 0 is to be compared and all others are ignored 0xE SSC 13 0 is to be compared and all others are ignored 0xF SSC 14 0 is to be compared and all others are ignored Note The bit 15 of synchronous counter SSC 15 in RTC_SS is never compared 23 15 Reserved Must be kept at reset value 14 0 SSC 14 0 Alarm sub second value This value is the alarm s...

Page 438: ...ng calibration and reference clock privilege protection When set RTC_SHIFTCTL RTC_COSC RTC_CTL registers can be w ritten only w hen the APB access is in privileged mode otherw ise w hether APB access is in privileged or non privileged mode can be w ritten the above registers Refer to Table 16 4 RTC privileged protected mode configuration summary 12 TAMPPRIP Tamper privilege protection excluding ba...

Page 439: ...PWSECP 1 from 0 to 128 BKPWSECP BKPRWSECP can be w ritten only w hen the APB is in secure mode They can be read in secure or non secure mode This zone is the protection zone B If TZEN 0 the protection zone B can be read and w ritten w ith non secure access Backup registers from RTC_BKPm m BKPWSECP from 0 to 127 can be read or w ritten w hen the APB is in secure or in non secure mode This zone is t...

Page 440: ...e APB access is in secured mode otherw ise w hether APB access is in secured or non secured mode can be w ritten the above configuration 11 4 Reserved Must be kept at reset value 3 TSSECP Timestamp protection When set timestamp configuration and interrupt clear can be w ritten only w hen the APB access is in secured mode otherw ise w hether APB access is in secured or non secured mode can be w rit...

Page 441: ... pin 15 5 Reserved Must be kept at reset value 4 TSOVRF Time stamp overflow flag This bit is set by hardw are w hen a time stamp event is detected if TSF bit is set before 3 TSF Time stamp flag Set by hardw are w hen time stamp event is detected 2 WTF Wakeup timer flag Set by hardw are w hen w akeup timer decreased to 0 This flag must be cleared at least 1 5 RTC Clock periods before WTF is set to ...

Page 442: ...r detection is found on tamper0 input pin 15 5 Reserved Must be kept at reset value 4 TSOVRNSMF Time stamp overflow non secure masked flag This bit is set by hardw are w hen a time stamp event is detected if TSF bit is set before 3 TSNSMF Time stamp flag Set by hardw are w hen time stamp event is detected 2 WTNSMF Wakeup timer non secure masked flag Set by hardw are w hen w akeup timer decreased t...

Page 443: ... 4 TSOVRSMF Time stamp overflow secure masked flag This bit is set by hardw are w hen a time stamp event is detected if TSF bit is set before 3 TSSMF Time stamp secure masked flag Set by hardw are w hen time stamp event is detected 2 WTSMF Wakeup timer secure masked flag Set by hardw are w hen w akeup timer decreased to 0 This flag must be cleared at least 1 5 RTC Clock periods before WTF is set t...

Page 444: ...r It is recommended to check and then clear TSOVRF only after clearing the TSF bit Otherw ise an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared 3 TSFC Timestamp flag clear Writing 1 in this bit clears the TSF bit in the RTC_STAT register 2 WTFC Wakeup timer flag clear Writing 1 in this bit clears the WTF bit in the RTC_STAT register 1 ALRM1FC Al...

Page 445: ...Descriptions 31 0 DATA 31 0 Data These registers can be w rote or read by softw are The content remains valid even in pow er saving mode because they can pow ered on by VBAT Tamper detection flag TPxF assertion w ill reset these registers ...

Page 446: ...tition CH Capture Compare 4 4 1 0 Complementary Dead time Break Single Pulse Quadrature Decoder Slave Controller Inter connection 1 2 DMA 3 Debug Mode 1 TIMER0 ITI0 0 ITI1 TIMER1_TRGO ITI2 TIMER2_TRGO ITI3 0 2 TIMER1 ITI0 TIMER0_TRGO ITI1 0 ITI2 TIMER2_TRGO ITI3 0 TIMER2 ITI0 TIMER0_TRGO ITI1 TIMER1_TRGO ITI2 0 ITI3 0 TIMER3 ITI0 TIMER0_TRGO ITI1 TIMER1_TRGO ITI2 TIMER2_TRGO ITI3 0 TIMER4 ITI0 TIM...

Page 447: ...on 17 1 2 Characteristics Total channel num 4 Counter width 16 bit Source of counter clock is selectable internal clock internal trigger external input external trigger Multiple counter modes count up count down count up down Quadrature Decoder used to track motion and determine both rotation direction and position Hall sensor for 3 phase motor control Programmable prescaler 16 bit The factor can ...

Page 448: ...CKM clock monitor CH0_O CH0_ON DMA controller TIMERx_TRGO DMA REQ ACK TIMERx_CH0 TIMERx_CH1 TIMERx_CH2 TIMERx_CH3 TIMERx_TG TIMERx_UP TIMERx_CMT Interrupt break update trig ctrl cap cmt CH1_O CH1_ON CH2_O CH2_ON CH3_O req en direct req set PSC PSC_CLK TIMER_CK ETIFP 17 1 4 Function overview Clock selection The advanced timer has the capability of being clocked by either the TIMER_CK or an alternat...

Page 449: ... the internal trigger input pin ITI0 1 2 3 This mode can be selectedby setting SMC 2 0 to 0x7 and the TRGS 2 0 to 0x0 0x1 0x2 or 0x3 SMC1 1 b1 external clock mode 1 External input is selected as timer clock source ETI The TIMER_CK which drives counter s prescaler to count can be triggered by the event of rising or falling edge on the external pin ETI This mode can be selected by setting the SMC1 b...

Page 450: ...be generated after TIMERx_CREP 1 times of overflow Otherwise the update event is generated each time when overflows The counting direction bit DIR in the TIMERx_CTL0 register should be set to 0 for the up counting mode Whenever if the update event software trigger is enabled by setting the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event...

Page 451: ... 63 62 61 00 01 02 03 CNT_CLK PSC_CLK Figure 17 5 Timing chart of up counting mode change TIMERx_CAR ongoing TIMER_CK CEN CNT_CLK PSC_CLK CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 05 06 07 Update event UPE Update interrupt flag UPIF Auto reload register 65 63 change CAR Vaule CNT_REG 5E 5F 60 61 62 63 64 65 00 01 02 62 63 00 Update event UPE Update interrupt flag UPIF Auto reload register 65 63 cha...

Page 452: ...ue will be initialized to the counter reload value and generates an update event If set the UPDIS bit in TIMERx_CTL0 register the update event is disabled When an update event occurs all the registers repetition counter auto reload register prescaler register are updated Figure 17 6 Timing chart of down counting mode PSC 0 1 and Figure 17 7 Timing chart of down counting mode change TIMERx_CAR ongo...

Page 453: ...e subtract 1 in the up counting direction and generates an underflow event when the counter counts to 1 in the down counting direction The counting direction bit DIR in the TIMERx_CTL0 register is read only and indicates the counting direction when in the center aligned mode The counting direction is updated by hardware automatically Setting the UPG bit in the TIMERx_SWEVG register will initialize...

Page 454: ...registers only after a given number N 1 of cycles of the counter where N is CREP in TIMERx_CREP register The repetition counter is decremented at each counter overflow in up counting mode at each counter underflow in down counting mode or at each counter overflow and at each counter underflow in center aligned mode Setting the UPG bit in the TIMERx_SWEVG register will reload the content of CREP in...

Page 455: ...low TIMERx_CREP 0x0 TIMER_CK 01 02 62 63 62 61 UPIF TIMERx_CREP 0x1 01 00 01 02 62 63 62 61 UPIF UPIF TIMERx_CREP 0x2 CNT_CLK Figure 17 10 Repetition counter timing chart of up counting mode CEN CNT_REG 60 61 62 63 00 01 62 63 00 01 62 63 Underflow Overflow TIMERx_CREP 0x0 TIMER_CK 00 01 62 63 00 01 UPIF TIMERx_CREP 0x1 62 63 00 01 62 63 00 01 UPIF UPIF TIMERx_CREP 0x2 CNT_CLK ...

Page 456: ...h outputs Each channel is built around a channel capture compare register including an input stage channel controller and an output stage Input capture mode Capture mode allows the channel to perform measurements such as pulse timing frequency period duty cycle and so on The input stage consists of a digital filter a channel polarity selection edge detection and a channel prescaler When a selected...

Page 457: ...xP One more selector is for the other channel and trig controlled by CHxMS The IC_prescaler make several the input event generate one effective capture event On the capture event TIMERx_CHxCV will restore the value of counter So the process canbe divided to several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal and requested signal quality configure ...

Page 458: ...de Figure 17 13 Output compare logic with complementary output x 0 1 2 Capture compare register CHxCV Counter output comparator Compare output control CHxCOMCTL CNT CHxCV CNT CHxCV CNT CHxCV Output complementary protection register Dead Time Output enable and polarity selector CHxP CHxNP CHxE CHxNE OxCPRE CHx_O CHx_ON Figure 17 14 Output compare logic CH3_O Capture compare register CH3CV Counter o...

Page 459: ... and frequency When thecounter matches the value in the TIMERx_CHxCV register of an output compare channel the channel n output can be set cleared or toggled basedonCHxCOMCTL Whenthecounterreaches thevalueintheTIMERx_CHxCV register the CHxIF bit is set and the channel n interrupt is generated if CHxIE 1 And the DMA request will be asserted if CxCDE 1 So the process canbe divided to several steps a...

Page 460: ...e counter mode we can also divide PWM into EAPWM Edge aligned PWM and CAPWM Centre aligned PWM The EAPWM period is determined by TIMERx_CAR and duty cycle is determined by TIMERx_CHxCV Figure 17 16 Timing chart of EAPWM shows the EAPWM output and interrupts waveform The CAPWM period is determined by 2 TIMERx_CAR and duty cycle is by 2 TIMERx_CHxCV Figure 17 17 Timing chart of CAPWM shows the CAPWM...

Page 461: ... CAM 2 b01 down only CAM 2 b10 up only CHxIF CAM 2 b11 up down CHxIF Channel output reference signal As is shown in Figure 17 13 Output compare logic with complementary output x 0 1 2 when the TIMERx is used in the compare match output mode the OxCPRE signal Channel x Output prepare signal is defined by setting the CHxCOMCTL filed The OxCPRE signal has several types ofoutput function Theseinclude ...

Page 462: ...o 0x04 0x05 Here the output can be forced to an inactive active level irrespective of the comparison condition between the counter and the TIMERx_CHxCV values The OxCPRE signal can be forced to 0 when the ETIFE signal is derived from the external ETI pin and when it is set to a high level by setting the CHxCOMCEN bit to 1 in the TIMERx_CHCTL0 register The OxCPRE signal will not return to its activ...

Page 463: ...RE CHxNP CHx_ON output enable 1 0 CHx_O OxCPRE CHxP CHx_O output enable CHx_ON LOW CHx_ON output disable 1 CHx_O OxCPRE CHxP CHx_O output enable CHx_ON OxCPRE CHxNP CHx_ON output enable 1 0 0 CHx_O CHxP CHx_O output disable CHx_ON CHxNP CHx_ON output disable 1 CHx_O CHxP CHx_O output enable CHx_ON OxCPRE CHxNP CHx_ON output enable 1 0 CHx_O OxCPRE CHxP CHx_O output enable CHx_ON CHxNP CHx_ON outpu...

Page 464: ...ctive value As show in the Figure17 18 Complementary outputwith dead time insertion The dead time delay is greater than or equal to the CHx_ON duty cycle then the CHx_ON signal is always the inactive value Figure 17 18 Complementary output with dead time insertion 0 CHxVAL CAR CxOPRE CHx_O CHx_ON Deadtime Corner case Deadtime pulse width CHx_O CHx_ON Deadtime Pulse width Deadtime A B Break functio...

Page 465: ...HxNP 0 ISOx ISOxN CHxEN 1 CHxNEN 0 CHxP 0 CHxNP 0 ISOx ISOxN Quadrature decoder The quadrature decoder function uses two quadrature inputs CI0 and CI1 derived from the TIMERx_CH0 and TIMERx_CH1 pins respectively to interact with each other to generate the counter value Setting SMC 0x01 0x02 or 0x03 to select that the counting direction of timer is determined only by the CI0 only by the CI1 or by t...

Page 466: ... CI0 and CI1 counting CI1FE1 High Dow n Up X X CI1FE1 Low Up Dow n X X CI0FE0 High X X Up Dow n CI0FE0 Low X X Dow n Up Note means no counting X means impossible Figure 17 20 Example of counter operation in encoder interface mode CI0 CI1 UP down Counter Figure 17 21 Example of encoderinterface mode with CI0FE0 polarity inverted CI0 CI1 UP down Counter Hall sensor function Hall sensoris generally u...

Page 467: ...ction so you can choose from Advanced General L0 TIMER And TIMER_out need have functions of complementary and Dead time so only advanced timer can be chosen Else based on the timers internal connection relationship pair s timers can be selected For example TIMER_in TIMER1 TIMER_out TIMER0 ITI1 After getting appropriate timers combination and wire connection we need to configure timers Some key set...

Page 468: ...he event mode which is selected by the SMC 2 0 in the TIMERx_SMCFG register The trigger input of these modes can be selected by the TRGS 2 0 in the TIMERx_SMCFG register Table 17 4 Examplesof slave mode Mode Selection Source Selection Polarity Selection Filter and Prescaler LIST SMC 2 0 3 b100 restart mode 3 b101 pause mode 3 b110 event mode TRGS 2 0 000 ITI0 001 ITI1 010 ITI2 011 ITI3 100 CI0F_ED...

Page 469: ...input comes TRGS 2 0 3 b000 ITI0 is selected For ITI0 no polarity selector can be used For the ITI0 no filter and prescaler can be used Figure 17 24 Restart mode TIMER_CK CEN CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 00 01 02 UPIF ITI0 TRGIF Internal sync delay Exam2 Pause mode The counter w ill be paused w hen the trigger input is low and it w illstart w hen the trigger input is high TRGS 2 0 3 b1...

Page 470: ...singsoftware SettingtheCENbit to1ora triggerfrom the triggersignals edgecangenerate a pulse and then keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software If the CEN bit is cleared to 0 using software the counter will be stopped and its value held If the CEN bit is automatically cleared to 0 by a hardware update event the counter will be reinitia...

Page 471: ...iguring another timer to be in the slave mode The following figures present several examples of trigger selection for the master and slave modes Figure 17 28 Timer0 master slave mode example shows the timer0 trigger selection when it is configured in slave mode Figure 17 28 Timer0 master slave mode example TIMER0 TIMER 1 Prescaler Counter Master mode control TIMER 2 Prescaler Counter Master mode c...

Page 472: ... TIMER2 TIMER0 starts counting from its current value with the divided internal clock after being triggered by TIMER2 enable signal output When TIMER0 receives the trigger signal its CEN bit is set automatically and the counter counts until TIMER0 is disabled Both clock frequency of the counters are divided by 3 from TIMER_CK fPSC_CLK fTIMER_CK 3 Steps are shown as follows 1 Configure TIMER2 in ma...

Page 473: ... signal of TIMER2 In this example TIMER0 is enabled with the enable signal of TIMER2 Refer to Figure 17 31 Pause mode of TIMER0 controlled by enable signal of TIMER2 TIMER0 counts with the divided internal clock only when TIMER2 is enabled Both clock frequency of thecounters are divided by 3 from TIMER_CK fPSC_CLK fTIMER_CK 3 Steps are shown as follows 1 Configure TIMER2 in master mode and output ...

Page 474: ...MERx_SMCFG register 5 Enable TIMER0 by writing 1 to the CEN bit TIMER0_CTL0 register 6 Start TIMER2 by writing 1 to the CEN bit TIMER2_CTL0 register Figure 17 32 Pause mode of TIMER0 controlled by O0CPREF signal of TIMER2 TIMER_CK CNT_REG TRGIF CNT_REG 60 O0CPRE 61 62 63 00 01 11 12 13 14 TIMER2 TIMER0 Using an external trigger to start two timers synchronously The start of TIMER0 is triggered by ...

Page 475: ..._DMACFG and TIMERx_DMATB Corresponding DMA request bit should be asserted to enable DMA request for internal interrupt event TIMERx will send a request to DMA when the interrupt event occurs DMA is configured to M2P memory to peripheral mode and the address of TIMERx_DMATB is configured to PADDR peripheral base address then DMA will access the TIMERx_DMATB In fact TIMERx_DMATB register is only a b...

Page 476: ...al 476 If one more DMA request event occurs TIMERx will repeat the process above Timer debug mode When the Cortex M33 halted and the TIMERx_HOLD configuration bit in DBG_CTL0 register is set to 1 the TIMERx counter stops ...

Page 477: ...ed by the dead time generators and the digital filters 00 fDTS fCK_TIMER 01 fDTS fCK_TIMER 2 10 fDTS fCK_TIMER 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns mode selection 00 No center aligned mode edge aligned mode The direction of the counter is specified...

Page 478: ...counter generates an overflow or underflow event The slave mode controller generates an update event 1 Only counter overflow underflow generates an update interrupt or DMA request 1 UPDIS Update disable This bit is used to enable or disable the update event generation 0 update event enable The update event is generate and the buffered registers are loaded w ith their preloaded values w hen one of ...

Page 479: ...e of channel 0 complementary output 0 When POEN bit is reset CH0_ON is set low 1 When POEN bit is reset CH0_ON is set high This bit can be modified only w hen PROT 1 0 bits in TIMERx_CCHP register is 00 8 ISO0 Idle state of channel 0 output 0 When POEN bit is reset CH0_O is set low 1 When POEN bit is reset CH0_O is set high The CH0_O output changes after a dead time if CH0_ON is implemented This b...

Page 480: ...Compare In this mode the master mode controller selects the O2CPRE signal is used as TRGO 111 Compare In this mode the master mode controller selects the O3CPRE signal is used as TRGO 3 DMAS DMA request source selection 0 DMA request of channel x is sent w hen capture compare event occurs 1 DMA request of channel x is sent w hen update event occurs 2 CCUC Commutation control shadow register update...

Page 481: ... mode or event mode But the TRGS bits must not be 3 b111 in this case The external clock input w ill be ETIF if external clock mode 0 and external clock mode 1 are enabled at the same time Note External clock mode 0 enable is in this register s SMC bit filed 13 12 ETPSC 1 0 External trigger prescaler The frequency of external trigger signal ETI must not be at higher than 1 4 of TIMER_CK frequency ...

Page 482: ...ITI0 001 Internal trigger input 1 ITI1 010 Internal trigger input 2 ITI2 011 Internal trigger input 3 ITI3 100 CI0 edge flag CI0F_ED 101 channel 0 input Filtered output CI0FE0 110 channel 1 input Filtered output CI1FE1 111 External trigger input filter output ETIFP These bits must not be changed w hen slave mode is enabled 3 Reserved Must be kept at reset value 2 0 SMC 2 0 Slave mode control 000 D...

Page 483: ...ed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRGDEN CMTDEN CH3DEN CH2DEN CH1DEN CH0DEN UPDEN BRKIE TRGIE CMTIE CH3IE CH2IE CH1IE CH0IE UPIE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 15 Reserved Must be kept at reset value 14 TRGDEN Trigger DMA request enable 0 disabled 1 enabled 13 CMTDEN Co...

Page 484: ...disabled 1 enabled 3 CH2IE Channel 2 capture compare interrupt enable 0 disabled 1 enabled 2 CH1IE Channel 1 capture compare interrupt enable 0 disabled 1 enabled 1 CH0IE Channel 0 capture compare interrupt enable 0 disabled 1 enabled 0 UPIE Update interrupt enable 0 disabled 1 enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed ...

Page 485: ...IF Break interrupt flag This flag is set by hardw are w hen the break input goes active and cleared by softw are if the break input is not active 0 No active level break has been detected 1 An active level has been detected 6 TRGIF Trigger interrupt flag This flag is set by hardw are on trigger event and cleared by softw are When the slave mode controller is enabled in all modes but pause mode an ...

Page 486: ...urred Software event generation register TIMERx_SWEVG Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BRKG TRGG CMTG CH3G CH2G CH1G CH0G UPG w w w w w w w w Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 BRKG Break event generatio...

Page 487: ...red by hardw are When this bit is set the CH0IF flag is set the corresponding interrupt or DMA request is sent if enabled In addition if channel 1 is configured in input mode the current value of the counter is captured in TIMERx_CH0CV register and the CH0OF flag is set if the CH0IF flag w as already high 0 No generate a channel 1 capture or compare event 1 Generate a channel 1 capture or compare ...

Page 488: ...d as input IS1 is connected to CI1FE1 10 Channel 1 is configured as input IS1 is connected to CI0FE1 11 Channel 1 is configured as input IS1 is connected to ITS This mode is w orking only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register 7 CH0COMCEN Channel 0 output compare clear enable When this bit is set the O0CPRE signal is cleared w hen High level is detected...

Page 489: ...nable The PWM mode can be used w ithout validating the shadow register only in single pulse mode SPM bit in TIMERx_CTL0 register is set This bit cannot be modified w hen PROT 1 0 bit filed in TIMERx_CCHP register is 11 and CH0MS bit filed is 00 2 CH0COMFEN Channel 0 output compare fast enable When this bit is set the effect of an event on the trigger in input on the capture compare output w illbe ...

Page 490: ...ignal and the length of the digital filter applied to CI0 0000 Filter disabled fSAMP fDTS N 1 0001 fSAMP fCK_TIMER N 2 0010 fSAMP fCK_TIMER N 4 0011 fSAMP fCK_TIMER N 8 0100 fSAMP fDTS 2 N 6 0101 fSAMP fDTS 2 N 8 0110 fSAMP fDTS 4 N 6 0111 fSAMP fDTS 4 N 8 1000 fSAMP fDTS 8 N 6 1001 fSAMP fDTS 8 N 8 1010 fSAMP fDTS 16 N 5 1011 fSAMP fDTS 16 N 6 1100 fSAMP fDTS 16 N 8 1101 fSAMP fDTS 32 N 5 1110 fS...

Page 491: ...Refer to CH0COMCTL description 11 CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description 10 CH3COMFEN Channel 3 output compare fast enable Refer to CH0COMSEN description 9 8 CH3MS 1 0 Channel 3 mode selection This bit field specifies the direction of the channel and the input signal selection This bit field is w ritable only w hen the channel is not active CH3EN bit in TIM...

Page 492: ...arger than TIMERx_CH0CV else active 111 PWM mode1 When counting up O0CPRE is inactive as long as the counter is smaller than TIMERx_CH0CV else active When counting dow n O0CPRE is active as long as the counter is larger than TIMERx_CH0CV else inactive When configured in PWM mode the O2CPRE level changes only w hen the output compare mode sw itches from Timing mode mode to PWM mode or w hen the res...

Page 493: ...as input IS2 is connected to ITS This mode is w orking only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register Input capture mode Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 CH3CAPFLT 3 0 Channel 3 input capture filter control Refer to CH0CAPFLT description 11 10 CH3CAPPSC 1 0 Channel 3 input capture prescaler Refer to CH0CAPPSC descri...

Page 494: ...trol register 2 TIMERx_CHCTL2 Address offset 0x20 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3NP Reserved CH3P CH3EN CH2NP CH2NEN CH2P CH2EN CH1NP CH1NEN CH1P CH1EN CH0NP CH0NEN CH0P CH0EN rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 16 Reserved ...

Page 495: ...s used to define the polarity of CI0 This bit cannot be modified w hen PROT 1 0 bit filed in TIMERx_CCHP register is 11 or 10 2 CH0NEN Channel 0 complementary output enable When channel 0 is configured in output mode setting this bit enables the complementary output in channel0 0 Channel 0 complementary output disabled 1 Channel 0 complementary output enabled 1 CH0P Channel 0 capture compare funct...

Page 496: ...pture event in channel0 0 Channel 0 disabled 1 Channel 0 enabled Counter register TIMERx_CNT Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CNT 15 0 This bit filed indicates t...

Page 497: ...e accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CARL 15 0 Counter auto reload value This bit filed specifies the auto reload value of the counter Counter repetition register TIMERx_CREP Address offset 0x30 Reset value 0x0000 0000 This regist...

Page 498: ... 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH0VAL 15 0 Capture or compare value of channel0 When channel 0 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 0 is configured in output mode this bit filed contains value to be compared to the counter When th...

Page 499: ...28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH2VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH2VAL 15 0 Capture or compare value of channel 2 When channel 2 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 2 is ...

Page 500: ...KP BRKEN ROS IOS PROT 1 0 DTCFG 7 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 POEN Primary output enable This bit s set by softw are or automatically by hardw are depending on the OAEN bit It is cleared asynchronously by hardw are as soon as the break input is active When one of channels is configured in output mode setting this bit enables the ...

Page 501: ...ode 0 When POEN bit is reset the channel output signals CHx_O CHx_ON are disabled 1 When POEN bit is reset he channel output signals CHx_O CHx_ON are enabled w ith relationship to CHxEN CHxNEN bits in TIMERx_CHCTL2 register This bit cannot be modified w hen PROT 1 0 bit filed in TIMERx_CCHP register is 10 or 11 9 8 PROT 1 0 Complementary register protect control This bit filed specifies the w rite...

Page 502: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DMATC 4 0 Reserved DMATA 4 0 rw rw Bits Fields Descriptions 31 13 Reserved Must be kept at reset value 12 8 DMATC 4 0 DMA transfer count This filed is defined the number of DMA w ill access R W the register of TIMERx_DMATB 7 5 Reserved Must be kept at reset value 4 0 DMATA 4 0 DMA transfer access st...

Page 503: ...ed by hardw are and ranges from 0 to DMATC Configuration register TIMERx_CFG Address offset 0xFC Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHVSEL OUTSEL rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 CHVSEL Write CHxVAL register selection...

Page 504: ...GD32W51x User Manual 504 ...

Page 505: ...TIMER3 4 32bit TIMER1 2 Source of count clock is selectable internal clock internal trigger external input external trigger Multiple counter modes count up count down count up down Quadrature decoder used to track motion and determine both rotation direction and position Hall sensor for 3 phase motor control Programmable prescaler 16 bit Factor can be changed on the go Each channel is user configu...

Page 506: ..._CK req en direct req set ETIFP 17 2 4 Function overview Clock selection The general level0 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC TIMERx_SMCFG bit 2 0 SMC 2 0 3 b000 Internal timer clock CK_TIMER which is from module RCU The default internal clock source is the CK_TIMER used to drive the counter prescaler when the slave mode...

Page 507: ...nalclock mode 1 External input pin source ETI The TIMER_CK which drives counter s prescaler to count can be triggered by the event of rising or falling edge on the external pin ETI This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1 The other way to select the ETI signal as the clock source is to set the SMC 2 0 to 0x7 and the TRGS 2 0 to 0x7 respectively Note that ...

Page 508: ...te event is generated at each counter overflow The counting direction bit DIR in the TIMERx_CTL1 register should be set to 0 for the up counting mode When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If the UPDIS bit in TIMERx_CTL0 register is set the update event is disabled When an update event occurs...

Page 509: ... 63 62 61 00 01 02 03 CNT_CLK PSC_CLK Figure 17 38 Timing chart of up counting mode change TIMERx_CAR ongoing TIMER_CK CEN CNT_CLK PSC_CLK CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 05 06 07 Update event UPE Update interrupt flag UPIF Auto reload register 65 63 change CAR Vaule CNT_REG 5E 5F 60 61 62 63 64 65 00 01 02 62 63 00 Update event UPE Update interrupt flag UPIF Auto reload register 65 63 ch...

Page 510: ...l be initialized to the counter reload value and generates an update event If the UPDIS bit in TIMERx_CTL0 register is set the update event is disabled When an update event occurs all the registers repetition counter auto reload register prescaler register are updated Figure 17 39 Timing chart of down counting mode PSC 0 1 and Figure 17 40 Timing chart of down counting mode change TIMERx_CAR ongoi...

Page 511: ...he counter counts to the counter reload value subtract 1 in the up counting direction and generates an underflow event when the counter counts to 1 in the down counting mode The counting direction bit DIR in the TIMERx_CTL0 register is read only and indicates the counting direction when in the center aligned mode The counting direction is updated by hardware automatically Setting the UPG bit in th...

Page 512: ... TIMERx_CTL0 CAM 2 b10 upcount only TIMERx_CTL0 CAM 2 b10 downcount only CHxIF Capture compare channels The general level0 Timer has four independent channels whichcanbeusedas captureinputs or compare match outputs Each channel is built around a channel capture compare register including an input stage channel controller and an output stage Input capture mode Capture mode allows the channel to per...

Page 513: ...of them by CHxP One more selector is for the other channel and trig controlled by CHxMS The IC_prescaler make several the input event generate one effective capture event On the capture event TIMERx_CHxCV will restore the value of Counter So the process can be divided to several steps as below Step1 Filter Configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal and requested signal qual...

Page 514: ...re 17 43 Output compare logic x 0 1 2 3 shows the logic circuit of output compare mode The relationship between the channel output signal CHx_O and the OxCPRE signal more details refer to Channel output reference signal is described as blew The active level of O0CPRE is high the output level of CH0_O depends on OxCPRE signal CHxP bit and CH0P bit please refer to the TIMERx_CHCTL2 register for more...

Page 515: ...hree compare modes toggle set clear CAR 0x63 CHxVAL 0x3 Figure 17 44 Output compare in three modes CEN CNT_REG 00 01 02 03 04 05 62 63 Overflow match toggle CNT_CLK OxCPRE 00 01 02 03 04 05 62 63 01 02 03 04 05 00 match set match clear OxCPRE OxCPRE PWM mode In the output PWM mode by setting the CHxCOMCTL bits to3 b110 PWM mode0 or to 3 b 111 PWM mode1 the channel can outputs PWM waveform accordin...

Page 516: ...theoutput will bealways activeunderPWM mode0 CHxCOMCTL 3 b110 And if TIMERx_CHxCV is equal to zero the output will be always inactive under PWM mode0 CHxCOMCTL 3 b110 Figure 17 45 Timing chart of EAPWM 0 CHxVAL CAR PWM MODE0 PWM MODE1 Cx OUT Cx OUT Interrupt signal CHxIF Figure 17 46 Timing chart of CAPWM 0 CHxVAL CAR PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF CAM 2 b01 down only CAM...

Page 517: ...of the comparison condition between the counter and the TIMERx_CHxCV values The OxCPRE signal can be forced to 0 when the ETIFE signal is derived from the external ETI pin and when it is set to a high level by setting the CHxCOMCEN bit to 1 in the TIMERx_CHCTL0 register The OxCPRE signal will not return to its active level until the next update event occurs Quadrature decoder The quadrature decode...

Page 518: ...ode CI0 CI1 UP down Counter Figure 17 48 Example of encoder interface mode with CI0FE0 polarity inverted CI0 CI1 UP down Counter Hall sensor function Refer to Advanced timer TIMERx x 0 Slave controller The TIMERx can be synchronized with a trigger in several modes including the restart mode the pause mode and the event mode which is selected by the SMC 2 0 in the TIMERx_SMCFG register The trigger ...

Page 519: ...figuring CHxCAPFLT no prescaler can be used For the ETIFP filter can be used by configuring ETFC and prescaler can be used by configuring ETPSC Exam1 Restart mode The counter w ill be cleared and restart w hen a rising edge of trigger input comes TRGS 2 0 3 b000 ITI0 is selected For ITI0 no polarity selector can be used For the ITI0 no filter and prescaler can be used Figure 17 49 Restart mode TIM...

Page 520: ...beclearandstopwhenthenext update event automatically In order to get pulse waveform you can set the TIMERx to PWM mode or compare by CHxCOMCTL Once the timer is set to operate in the single pulse mode it is not necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter The trigger to generate a pulse can be sourced from the trigger signals edge or by setting t...

Page 521: ... counter stop Timers interconnection Refer to Advanced timer TIMERx x 0 Timer DMAmode Timer s DMA mode is the function that configures timer s register by DMA module The relative registers are TIMERx_DMACFG and TIMERx_DMATB Of course you have to enable a DMA request which will be asserted by some internal interrupt event When the interrupt event was asserted TIMERxwill sendarequest toDMA whichis c...

Page 522: ...GD32W51x User Manual 522 Timer debug mode When the Cortex M33 halted and the TIMERx_HOLD configuration bit in DBG_CTL0 register set to 1 the TIMERx counter stops ...

Page 523: ... 1 0 ARSE CAM 1 0 DIR SPM UPS UPDIS CEN rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 10 Reserved Must be kept at reset value 9 8 CKDIV 1 0 Clock division The CKDIV bits can be configured by softw are to specify division ratio betw een the timer clock TIMER_CK and the dead time and sampling clock DTS w hich is used by the dead time generators and the digital filters 00 fDTS fCK_TIMER 01 fDTS...

Page 524: ...ate event 1 The CEN is cleared by hardw are and the counter stops at next update event 2 UPS Update source This bit is used to select the update event sources by softw are 0 When enabled any of the follow ing events generate an update interrupt or DMA request The UPG bit is set The counter generates an overflow or underflow event The slave mode controller generates an update event 1 When enabled o...

Page 525: ...onization function 000 Reset When the UPG bit in the TIMERx_SWEVG register is set or a reset is generated by the slave mode controller a TRGO pulse occurs And in the latter case the signal on TRGO is delayed compared to the actual reset 001 Enable This mode is usefulto start several timers at the same time or to control a w indow in w hich a slave timer is enabled In this mode the master mode cont...

Page 526: ... rw rw rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 ETP External trigger polarity This bit specifies the polarity of ETI signal 0 ETI is active at high level or rising edge 1 ETI is active at low level or falling edge 14 SMC1 Part of SMC for enable External clock mode1 In external clock mode 1 the counter is clocked by any active edge on the ETIF signal 0 Exte...

Page 527: ...6 0101 fSAMP fDTS 2 N 8 0110 fSAMP fDTS 4 N 6 0111 fSAMP fDTS 4 N 8 1000 fSAMP fDTS 8 N 6 1001 fSAMP fDTS 8 N 8 1010 fSAMP fDTS 16 N 5 1011 fSAMP fDTS 16 N 6 1100 fSAMP fDTS 16 N 8 1101 fSAMP fDTS 32 N 5 1110 fSAMP fDTS 32 N 6 1111 fSAMP fDTS 32 N 8 7 MSM Master slave mode This bit can be used to synchronize selected timers to begin counting at the same time The TRGI is used as the start event and...

Page 528: ... edge of the selected trigger input 101 Pause mode The trigger input enables the counter clock w hen it is high and disables the counter w hen it is low 110 Event mode A rising edge of the trigger input enables the counter The counter cannot be disabled by the slave mode controller 111 External clock mode0 The counter counts on the rising edges of the selected trigger DMAand interrupt enable regis...

Page 529: ... 7 Reserved Must be kept at reset value 6 TRGIE Trigger interrupt enable 0 disabled 1 enabled 5 Reserved Must be kept at reset value 4 CH3IE Channel 3 capture compare interrupt enable 0 disabled 1 enabled 3 CH2IE Channel 2 capture compare interrupt enable 0 disabled 1 enabled 2 CH1IE Channel 1 capture compare interrupt enable 0 disabled 1 enabled 1 CH0IE Channel 0 capture compare interrupt enable ...

Page 530: ...lag is set by hardw are w hen a capture event occurs w hile CH0IF flag has already been set This flag is cleared by softw are 0 No over capture interrupt occurred 1 Over capture interrupt occurred 8 7 Reserved Must be kept at reset value 6 TRGIF Trigger interrupt flag This flag is set by hardw are on trigger event and cleared by softw are When the slave mode controller is enabled in all modes but ...

Page 531: ... event generation register TIMERx_SWEVG Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRGG Reserved CH3G CH2G CH1G CH0G UPG w w w w w w Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 TRGG Trigger event generation This bit is set...

Page 532: ...s bit is set the counter is cleared if the center aligned or up counting mode is selected else dow n counting it takes the auto reload value The prescaler counter is cleared at the same time 0 No generate an update event 1 Generate an update event Channel control register 0 TIMERx_CHCTL0 Address offset 0x18 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 2...

Page 533: ...drives CH0_O O0CPRE is active high w hile CH0_O active level depends on CH0P bits 000 Timing mode The O0CPRE signal keeps stable independent of the comparison betw een the register TIMERx_CH0CV and the counter TIMERx_CNT 001 Set the channel output O0CPRE signal is forced high w hen the counter matches the output compare register TIMERx_CH0CV 010 Clear the channel output O0CPRE signal is forced low...

Page 534: ... edge on the trigger input to activate CH0_O output is 3 clock cycles 1 0 CH0MS 1 0 Channel 0 I O mode selection This bit field specifies the w orkmode of the channel and the input signal selection This bit field is w ritable only w hen the channel is not active CH0EN bit in TIMERx_CHCTL2 register is reset 00 Channel 0 is configured as output 01 Channel 0 is configured as input IS0 is connected to...

Page 535: ...nput The prescaler is reset w hen CH0EN bit in TIMERx_CHCTL2 register is clear 00 Prescaler disable capture is done on each channel input edge 01 Capture is done every 2 channel input edges 10 Capture is done every 4 channel input edges 11 Capture is done every 8 channel input edges 1 0 CH0MS 1 0 Channel 0 mode selection Same as Output compare mode Channel control register 1 TIMERx_CHCTL1 Address ...

Page 536: ... an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register 7 CH2COMCEN Channel 2 output compare clear enable When this bit is set the O2CPRE signal is cleared w hen High level is detected on ETIF input 0 Channel 2 output compare clear disable 1 Channel 2 output compare clear enable 6 4 CH2COMCTL 2 0 Channel 2 compare output control This bit field controls the behavior of the...

Page 537: ...of an event on the trigger in input on the capture compare output w illbe accelerated if the channel is configured in PWM0 or PWM1 mode The output channel w ill treat an active edge on the trigger input as a compare match and CH2_O is set to the compare level independently from the result of the comparison 0 Channel 2 output quickly compare disable The minimum delay from an edge on the trigger inp...

Page 538: ...MP fDTS 2 N 8 0110 fSAMP fDTS 4 N 6 0111 fSAMP fDTS 4 N 8 1000 fSAMP fDTS 8 N 6 1001 fSAMP fDTS 8 N 8 1010 fSAMP fDTS 16 N 5 1011 fSAMP fDTS 16 N 6 1100 fSAMP fDTS 16 N 8 1101 fSAMP fDTS 32 N 5 1110 fSAMP fDTS 32 N 6 1111 fSAMP fDTS 32 N 8 3 2 CH2CAPPSC 1 0 Channel 2 input capture prescaler This bit field specifies the factor of the prescaler on channel 2 input The prescaler is reset w hen CH2EN b...

Page 539: ...tput polarity Refer to CH0NP description 10 Reserved Must be kept at reset value 9 CH2P Channel 2 capture compare function polarity Refer to CH0P description 8 CH2EN Channel 2 capture compare function enable Refer to CH0EN description 7 CH1NP Channel 1 complementary output polarity Refer to CH0NP description 6 Reserved Must be kept at reset value 5 CH1P Channel 1 capture compare function polarity ...

Page 540: ...ing edge are both the active signal for capture or trigger operation in slave mode And CIxFE0 w illbe not inverted 0 CH0EN Channel 0 capture compare function enable When channel 0 is configured in output mode setting this bit enables CH0_O signal in active state When channel 0 is configured in input mode setting this bit enables the capture event in channel0 0 Channel 0 disabled 1 Channel 0 enable...

Page 541: ...0 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 PSC 15 0 Prescaler value of the counter clock The PSC clock is divided by PSC 1 to generate the counter clock The value of this bit filed w ill be loaded to the corr...

Page 542: ...7 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CARL 15 0 Counter auto reload value This bit filed specifies the auto reload value of the counter Channel 0 capture compare value register TIMERx_CH0CV x 1 2 Address offset 0x34 Reset value 0x0000 0000 This register has to be access...

Page 543: ...6 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH0VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH0VAL 15 0 Capture or compare value of channel0 When channel 0 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 0 is configured in output mode this bit fil...

Page 544: ...6 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH1VAL 15 0 Capture or compare value of channel1 When channel 1 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 1 is configured in output mode this bit fil...

Page 545: ...6 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH2VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH2VAL 15 0 Capture or compare value of channel 2 When channel 2 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 2 is configured in output mode this bit fi...

Page 546: ... Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH3VAL 15 0 Capture or compare value of channel 3 When channel3 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 3 is configured in output mode this bit file...

Page 547: ..._CTL0 5 b0_0001 TIMERx_CTL1 In a w ord Start Address TIMERx_CTL0 DMASAR 4 DMAtransfer buffer register TIMERx_DMATB Address offset 0x4C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMATB 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 DMATB 15 0 ...

Page 548: ...onnected to RTC w akeup 5 0 Reserved Must be kept at reset value Configuration register TIMERx_CFG Address offset 0xFC Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHVSEL Reserved rw Bits Fields Descriptions 15 2 Reserved Must be kept at reset value 1 CHVSEL Write CHxV...

Page 549: ...ther timers Timer also includes a dead time Insertion module which is suitable for motor control applications 17 3 2 Characteristics Total channel num 1 Counter width 16 bits Source of counter clock internal clock Counter modes count up only Programmable prescaler 16 bit The factor can be changed on the go Each channel is user configurable input capture mode output compare mode programmable PWM mo...

Page 550: ...rol deadtime insertion break input output mask and polarity control BKEN BRKIN CKM clock monitor CH0_O CH0_ON DMA controller DMA REQ ACK TIMERx_CH0 TIMERx_UP cap cmt req en direct req set PSC PSC_CLK TIMER_CK Interrupt break update 17 3 4 Function overview Clock selection The general level4 TIMER can only being clocked by the CK_TIMER Internal timer clock CK_TIMER which is from module RCU The gene...

Page 551: ... divide the timer clock TIMER_CK to a counter clock PSC_CLK by any factor between 1 and 65536 It is controlled by prescaler register TIMERx_PSC which can be changed on the go but is taken into account at the next update event Figure 17 55 Countertiming diagram with prescaler division change from 1 to 2 TIMER_CK CEN PSC_CLK CNT_REG Reload Pulse Prescaler CNT Prescaler BUF F7 F8 F9 FA FB FC 01 02 03...

Page 552: ...ger is enabled by setting the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If set the UPDIS bit in TIMERx_CTL0 register the update event is disabled When an update event occurs all the registers repetition counter auto reload register prescaler register are updated Figure 17 56 Up counter timechart PSC 0 1 show some examples of the c...

Page 553: ...eload register 65 63 change CAR Vaule 65 63 Auto reload shadow register Hardware set Hardware set Software clear Hardware set ARSE 0 ARSE 1 Repetition counter Counter repetition is used to generator update event or updates the timer registers only after a given number N 1 of cycles of the counter where N is CREP in TIMERx_CREP register The repetition counter is decremented at each counter overflow...

Page 554: ...ts Each channel is built around a channel capture compare register including an input stage channel controller and an output stage Input capture mode Capture mode allows the channel to perform measurements such as pulse timing frequency period duty cycle and so on The input stage consists of a digital filter a channel polarity selection edge detection and a channel prescaler When a selected edge o...

Page 555: ...fective capture event On the capture event CHxVAL will restore the value of Counter So the process can be divided to several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal and requested signal quality configure compatible CHxCAPFLT Step2 Edge selection CHxP CHxNP in TIMERx_CHCTL2 Rising or falling edge choose one by CHxP CHxNP Step3 Capture source se...

Page 556: ...of OxCPRE is active high level the output of CHx_O is active high level If the output of OxCPRE is inactive low level the output of CHx_O is active low level 2 Configure CHxNP 0 theactivelevel of CHx_ONis low contrary toOxCPRE CHxNE 1 the output of CHx_ON is enabled If the output of OxCPRE is active high level the output of CHx_O is active low level If the output of OxCPRE is inactive low level th...

Page 557: ...s toggle set clear CAR 0x63 CHxVAL 0x3 Figure 17 61 Output compare under three modes CEN CNT_REG 00 01 02 03 04 05 62 63 Overflow match toggle CNT_CLK OxCPRE 00 01 02 03 04 05 62 63 01 02 03 04 05 00 match set match clear OxCPRE OxCPRE PWM mode In the output PWM mode by setting the CHxCOMCTL bits to 3 b110 PWM mode0 or to 3 b 111 PWM mode1 the channel can generate PWM waveform according to the TIM...

Page 558: ...ter value matches the content of the TIMERx_CHxCV register The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06 0x07 In these modes the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content With regard to a more detail description re...

Page 559: ... 0 0 CHx_O CHxP CHx_ON CHxNP CHx_O CHx_ON output disable 1 CHx_O CHxP CHx_ON CHxNP CHx_O CHx_ON output enable If clock is enable CHx_O ISOx CHx_ON ISOxN 1 0 1 1 0 0 1 0 0 CHx_O CHx_ON LOW CHx_O CHx_ON output disable 1 CHx_O LOW CHx_O output disable CHx_ON OxCPRE CHxNP CHx_ON output enable 1 0 CHx_O OxCPRE CHxP CHx_O output enable CHx_ON LOW CHx_ON output disable 1 CHx_O OxCPRE CHxP CHx_O output en...

Page 560: ...cleared CHx_O signal will be cleared at once while CHx_ON signal remains at the low value until the end of the dead time delay Sometimes we can see corner cases about the dead time insertion For example The dead time delay is greater than or equal to the CHx_O duty cycle then the CHx_O signal is always the inactive value as show in the Figure 17 63 Complementary output with dead time insertion The...

Page 561: ...ter is set If BRKIE is 1 an interrupt generated Figure 17 64 Output behavior in response to a break The breakhigh active OxCPRE CHx_O CHx_ON BRKIN CHx_O CHx_ON CHx_O CHx_ON ISOx ISOxN ISOx ISOxN CHxEN 1 CHxNEN 1 CHxP 0 CHxNP 0 ISOx ISOxN CHxEN 1 CHxNEN 0 CHxP 0 CHxNP 0 ISOx ISOxN CHxEN 1 CHxNEN 0 CHxP 0 CHxNP 0 ISOx ISOxN Single pulse mode Single pulse mode is opposite to the repetitive mode which...

Page 562: ... mode and the trigger source is derived from the trigger signal Figure 17 65 Single pulse mode TIMERx_CHxCV 0x04 TIMERx_CAR 0x60 TIMER_CK CNT_CLK CEN CNT_REG 00 01 02 03 04 05 5F 60 00 O2CPRE CI3 Under SPM counter stop Timer DMAmode Timer s DMAmodeis thefunctionthat configurestimer s registerby DMAmodule Therelative registers areTIMERx_DMACFGandTIMERx_DMATB Ofcourse youhavetoenable aDMA request wh...

Page 563: ...GD32W51x User Manual 563 Timer debug mode When the Cortex M33 halted and the TIMERx_HOLD configuration bit in DBG_CTL1 register set to 1 the TIMERx counter stops ...

Page 564: ...KDIV 1 0 Clock division The CKDIV bits can be configured by softw are to specify division ratio betw een the timer clock TIMER_CK and the dead time and sampling clock DTS w hich is used by the dead time generators and the digital filters 00 fDTS fCK_TIMER 01 fDTS fCK_TIMER 2 10 fDTS fCK_TIMER 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1...

Page 565: ...lave mode controller generates a hardw are reset event 0 CEN Counter enable 0 Counter disable 1 Counter enable The CEN bit must be set by softw are w hen timer w orks in external clock pause mode and encoder mode While in event mode the hardw are can set the CEN bit automatically Control register 1 TIMERx_CTL1 Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 ...

Page 566: ...set or a rising edge of TRGI occurs When a channel does not have a complementary output this bit has no effect 1 Reserved Must be kept at reset value 0 CCSE Commutation control shadow enable 0 The shadow registers for CHxEN CHxNEN and CHxCOMCTL bits are disabled 1 The shadow registers for CHxEN CHxNEN and CHxCOMCTL bits are enabled After these bits have been w ritten they are updated based w hen c...

Page 567: ...1 enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH0OF Reserved BRKIF Reserved CMTIF Reserved CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31 10 Reserved Must be kept at reset value 9 CH...

Page 568: ...erved Must be kept at reset value 1 CH0IF Channel 0 s capture compare interrupt flag This flag is set by hardw are and cleared by softw are When channel 0 is in input mode this flag is set w hen a capture event occurs When channel 0 is in output mode this flag is set w hen a compare event occurs 0 No Channel 0 interrupt occurred 1 Channel 0 interrupt occurred 0 UPIF Update interrupt flag This bit ...

Page 569: ...rder to generate a capture or compare event in channel 0 it is automatically cleared by hardw are When this bit is set the CH0IF flag is set the corresponding interrupt or DMA request is sent if enabled In addition if channel 1 is configured in input mode the current value of the counter is captured in TIMERx_CH0CV register and the CH0OF flag is set if the CH0IF flag w as already high 0 No generat...

Page 570: ...Force high O0CPRE is forced high level 110 PWM mode0 When counting up O0CPRE is active as long as the counter is smaller than TIMERx_CH0CV else inactive When counting dow n O0CPRE is inactive as long as the counter is larger than TIMERx_CH0CV else active 111 PWM mode1 When counting up O0CPRE is inactive as long as the counter is smaller than TIMERx_CH0CV else active When counting dow n O0CPRE is a...

Page 571: ... w ritable only w hen the channel is not active CH0EN bit in TIMERx_CHCTL2 register is reset 00 Channel 0 is configured as output 01 Channel 0 is configured as input IS0 is connected to CI0FE0 10 Reserved 11 Channel 0 is configured as input IS0 is connected to ITS This mode is w orking only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register Input capture mode Bits ...

Page 572: ...is register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH0NP CH0NEN CH0P CH0EN rw rw rw rw Bits Fields Descriptions 31 4 Reserved Must be kept at reset value 3 CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode this bit specifies the complementary output signal pola...

Page 573: ...NP 1 CH0P 1 CIxFE0 s falling and rising edge are both the active signal for capture or trigger operation in slave mode And CIxFE0 w illbe not inverted This bit cannot be modified w hen PROT 1 0 bit filed in TIMERx_CCHP register is 11 or 10 0 CH0EN Channel 0 capture compare function enable When channel 0 is configured in output mode setting this bit enables CH0_O signal in active state When channel...

Page 574: ...nter clock The PSC clock is divided by PSC 1 to generate the counter clock The value of this bit filed w ill be loaded to the corresponding shadow register at every update event Counter auto reload register TIMERx_CAR Address offset 0x2C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 575: ...bit filed w hen these shadow registers are enabled Channel 0 capture compare value register TIMERx_CH0CV Address offset 0x34 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH0VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH0VAL 15 0 Capture ...

Page 576: ...Hx_ON if the corresponding enable bits CHxEN CHxNEN in TIMERx_CHCTL2 register have been set 0 Channel outputs are disabled or forced to idle state 1 Channel outputs are enabled 14 OAEN Output automatic enable This bit specifies w hether the POEN bit can be set automatically by hardw are 0 POEN can be not set by hardw are 1 POEN can be set by hardw are automatically at the next update event if the ...

Page 577: ...sters 00 protect disable No w rite protection 01 PROT mode 0 The ISOx ISOxN bits in TIMERx_CTL1 register and the BRKEN BRKP OAEN DTCFG bits in TIMERx_CCHP register are w riting protected 10 PROT mode 1 In addition of the registers in PROT mode 0 the CHxP CHxNP bits in TIMERx_CHCTL2 register if related channel is configured in output mode and the ROS IOS bits in TIMERx_CCHP register are w riting pr...

Page 578: ...ved Must be kept at reset value 4 0 DMATA 4 0 DMA transfer access start address This filed define the first address for the DMA access the TIMERx_DMATB When access is done through the TIMERx_DMA address first time this bit field specifies the address you just access And then the second access to the TIMERx_DMATB you w ill access the address of start address 0x4 5 b0_0000 TIMERx_CTL0 5 b0_0001 TIME...

Page 579: ...t 0xFC Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHVSEL OUTSEL rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 CHVSEL Write CHxVAL register selection This bit field set and reset by softw are 1 If w rite the CHxVAL register the w rite valu...

Page 580: ...ure17 66 Basictimerblock diagramprovides details ontheinternal configurationofthebasic timer Figure 17 66 Basic timer block diagram PSC Trigger processor Trigger Selector Counter Counter Register Interrupt Register set and update Interrupt collector APB BUS CK_TIMER CAR TIMERx_TRGO Interrupt Update UPIE TIMER_CK PSC_CLK DMA controller DMA REQ ACK TIMERx_UP 17 4 4 Function overview Clock selection ...

Page 581: ...vide the timer clock TIMER_CK to the counter clock PSC_CLK by any factor between 1 and 65536 It is controlled through prescaler register TIMERx_PSC which can be changed on the go but be taken into account at thenext update event Figure 17 68 Countertiming diagram with prescaler division change from 1 to 2 TIMER_CK CEN PSC_CLK CNT_REG Reload Pulse Prescaler CNT Prescaler BUF F7 F8 F9 FA FB FC 01 02...

Page 582: ...ster the counter value will be initialized to 0 and generates an update event If set the UPDIS bit in TIMERx_CTL0 register the update event is disabled When an update event occurs all the registers repetition counter auto reload register prescaler register are updated The following figures show some examples of the counter behavior for different clock prescaler factor when TIMERx_CAR 0x63 Figure 1...

Page 583: ... Auto reload register 65 63 change CAR Vaule CNT_REG 5E 5F 60 61 62 63 64 65 00 01 02 62 63 00 Update event UPE Update interrupt flag UPIF Auto reload register 65 63 change CAR Vaule 65 63 Auto reload shadow register Hardware set Hardware set Software clear Hardware set ARSE 0 ARSE 1 Timer debug mode When the Cortex M33 halted and the TIMERx_HOLD configuration bit in DBG_CTL0 register set to 1 the...

Page 584: ... 6 4 Reserved Must be kept at reset value 3 SPM Single pulse mode 0 Counter continues after update event 1 The CEN is cleared by hardw are and the counter stops at next update event 2 UPS Update source This bit is used to select the update event sources by softw are 0 When enabled any of the follow ing events generate an update interrupt or DMA request The UPG bit is set The counter generates an o...

Page 585: ...MC 2 0 Reserved rw Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 4 MMC 2 0 Master mode control These bits control the selection of TRGO signal w hich is sent in master mode to slave timers for synchronization function 000 Reset When the UPG bit in the TIMERx_SWEVG register is set or a reset is generated by the slave mode controller a TRGO pulse occurs And in the latter case ...

Page 586: ... Descriptions 31 9 Reserved Must be kept at reset value 8 UPDEN Update DMA request enable 0 disabled 1 enabled 7 1 Reserved Must be kept at reset value 0 UPIE Update interrupt enable 0 disabled 1 enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12...

Page 587: ... reset value 0 UPG This bit can be set by softw are and cleared by hardw are automatically When this bit is set the counter is cleared The prescaler counter is cleared at the same time 0 No generate an update event 1 Generate an update event Counter register TIMERx_CNT Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 588: ...he PSC clock is divided by PSC 1 to generate the counter clock The value of this bit filed w ill be loaded to the corresponding shadow register at every update event Counter auto reload register TIMERx_CAR Address offset 0x2C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15...

Page 589: ...flow control protocol CTS RTS The data frame can be transferred from LSB or MSB bit The polarity of the TX RX pins can be configured independently and flexibly All USARTs support DMA function for high speed data communication 18 2 Characteristics NRZ standard format Asynchronous full duplex communication Half duplex single wire communications Receive FIFO function Dual clock domain Asynchronous PC...

Page 590: ...ty RBNE receive FIFO full RFF Transmit buffer empty TBE transfer complete TC Flags for error detection overrun error ORERR noise error NERR frame error FERR and parity error PERR Flag for hardware flow control CTS changes CTSF Flag for LIN mode LIN break detected LBDF Flag for multiprocessor communication IDLE frame detected IDLEF Flag for ModBus communication Address character match AMF and recei...

Page 591: ...ift Register Receive Shift Register USART Control Registers CK Transimit Controler Hardware Flow Controler nRTS nCTS Receiver Controler USART Address Wakeup Unit USART Guard Time and Prescaler Register USART Status Register USART Interrupt Controler USARTDIV 8 2 OVSMOD USART Baud Rate Register UCLK Transmitter clock Receiver clock Write Buffer Read Buffer Read FiFO 18 3 1 USART frame format The US...

Page 592: ...owed by the configured number of stop bits The transfer speed of a USART frame depends on the frequency of the UCLK the configuration of the baud rate generator and the oversampling mode 18 3 2 Baud rate generation The baud rate divider is a 16 bit number which consists of a 12 bit integer and a 4 bit fractional part The number formed by these two values is used by the baud rate generator to deter...

Page 593: ...nsmit shift register If a data is written to the USART_TDATA register while a transmission is ongoing it will be firstly stored in the transmit buffer and transferred to the transmit shift register after the current transmission is done If a data is written to the USART_TDATA register while no transmission is ongoing the TBE bit will be cleared and set soon because the data will be transferred to ...

Page 594: ...fer communication is selected 4 Set the baud rate in USART_BAUD 5 Set the UEN bit in USART_CTL0 to enable the USART 6 Set the REN bit in USART_CTL0 After being enabled the receiver receives a bit stream after a valid start pulse has been detected Detection on noisy error parity error frame error and overrun error is performed during the reception of a frame When a frame is received the RBNE bit in...

Page 595: ...R bit in USART_STAT register will be set An interrupt is generated if the PERRIE bit in USART_CTL0 register is set If the RX pin is evaluated as 0 during a stop bit the frame error FERR bit in USART_ST AT register will be set An interrupt is generated If the receive DMA is enabled and the ERRIE bit in USART_CTL2 register is set When a frame is received if the RBNE bit is not cleared yet the last f...

Page 596: ...iority etc Clear the TC bit in USART_STAT Enable the DMA channel for USART Wait the TC bit to be set After all of the data frames are transmitted the TC bit in USART_STAT is set An interrupt occurs if the TCIE bit in USART_CTL0 is set When DMA is used for USART reception DMA transfers data from the receive data buffer of the USART to the internal SRAM The configuration steps are shown in Figure 18...

Page 597: ...annel for USART When the number of the data received by USART reaches the DMA transfer number an end of transfer interrupt can be generated in the DMA module 18 3 6 Hardware flow control The hardware flow control function is realized by the nCTS and nRTS pins The RTS flow control is enabled by writing 1 to the RTSEN bit in USART_CTL2 and the CTS flow control is enabled by writing 1 to the CTSEN bi...

Page 598: ...ature which is enabled by setting bit DEM in the USART_CTL2 control register allows the user to activate the external transceiver control through the DE Driver Enable signal The assertion time which is programmed usingthe DEA 4 0 bits field in the USART_CTL0 control register is the time between the activation of the DE signal and the beginning of the START bit The de assertion time which is progra...

Page 599: ... set and the receive frame is a 7bit data the LSB 6 bits will be compared withADDR 5 0 If the ADDM bit is set and the receive frame is a 9bit data the LSB 8 bits will be compared withADDR 7 0 18 3 8 LIN mode The local interconnection network mode is enabled by setting the LMEN bit in USART_CTL1 The CKEN STB 1 0 bit in USART_CTL1 and the SCEN HDEN IREN bits in USART_CTL2 should be cleared in LIN mo...

Page 600: ...ent through the CK pin during the transmission of the start bit and stop bit The CLEN bit in USART_CTL1 can be used to determine whether the clock is output or not during the last address flag bit transmission The clock output is also not activated during idle and break frame sending The CPH bit in USART_CTL1 can be used to determine whether data is captured on the first or the second clock edge T...

Page 601: ...oder and transmitted to theinfrared LED through the TXpin The SIR receive decoder receives the modulated signal from the infrared LED through the RX pin and puts the demodulated data frame totheUSARTreceiver The baud rateshouldnot be largerthan115200 for the encoder Figure 18 13 IrDA SIR ENDEC module Normal USART Transmit Encoder Receive Decoder SIR MODULE TX RX TX pin RX pin IREN 1 0 0 1 Infrared...

Page 602: ...ode The half duplex communication mode is enabled by setting the HDEN bit in USART_CTL2 The LMEN CKEN bits in USART_CTL1 and SCEN IREN bits in USART_CTL2 should be cleared in half duplex communication mode Only one wire is used in half duplex mode The TX and RX pins are connected together internally The TX pin should be configured as IO pin The conflicts should be controlled by the software When t...

Page 603: ...op bits The USART can automatically resend data according to the protocol for SCRTNUM times An interframe gap of 2 5 bits time will be inserted before the start of a resented frame At the end of the last repeated character the TC bit is set immediately without guard time The USART will stop transmitting and assert the frame error status if it still receives the NACK signal after the programmed num...

Page 604: ...ter field must be programmed to the minimum value 0x0 before the start of the block when using DMA mode With this value an interrupt is generated after the 4th received character The software must read the third byte as block lengthfrom the receive buffer In interrupt driven receive mode the length of the block may be checked by software or by programming the BL value However before the start of t...

Page 605: ...ster must be set The USART_RT register must be set to the value corresponding to a timeout of 2 characters time After the last stop bit is received when the receive line is idle for this duration an interrupt will be generated informing the software that the current block reception is completed In the ModBus ASCII mode the end of a block is recognized by a specific CR LF character sequence The USA...

Page 606: ... disabled before entering Deep sleep mode Before enteringDeep sleep mode software must check that the USART is not performing a transfer by checking the BSY flag in the USART_STAT register The REA bit must be checked to ensure the USART is actually enabled When the wakeup event is detected the WUF flag is set by hardware and a wakeup interrupt is generated if the WUIE bit is set independently of w...

Page 607: ...are ORed together before being sent to the interrupt controller so the USART can only generate a single interrupt request to the controller at any given time Software can service multiple interrupt events in a single interrupt service routine Figure 18 17 USART interrupt mapping diagram IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE WUF WUIE LBDF LBDIE AMF AMIE RTF RTIE EBF EBIE FERR NERR ORERR...

Page 608: ... Reserved Must be kept at reset value 27 EBIE End of Block interrupt enable 0 End of Block interrupt is disabled 1 End of Block interrupt is enabled This bit is reserved in USART1 26 RTIE Receiver timeout interrupt enable 0 Receiver timeout interrupt is disabled 1 Receiver timeout interrupt is enabled This bit is reserved in USART1 25 21 DEA 4 0 Driver Enable assertion time These bits are used to ...

Page 609: ... 0 Idle Line 1 Address Mark This bit field cannot be w ritten w hen the USART is enabled UEN 1 10 PCEN Parity control enable 0 Parity control disabled 1 Parity control enabled This bit field cannot be w ritten w hen the USART is enabled UEN 1 9 PM Parity mode 0 Even parity 1 Odd parity This bit field cannot be w ritten w hen the USART is enabled UEN 1 8 PERRIE Parity error interrupt enable 0 Parit...

Page 610: ...ode 0 USART not able to w ake up the MCU from Deep sleep mode 1 USART able to w ake up the MCU from Deep sleep mode Providing that the clock source for the USART must be IRC16M or LXTAL This bit is reserved in USART1 0 UEN USART enable 0 USART prescaler and outputs disabled 1 USART prescaler and outputs enabled 18 4 2 Control register 1 USART_CTL1 Address offset 0x04 Reset value 0x0000 0000 This r...

Page 611: ...xxxxxx frame format 10 Reserved 11 Reserved This bit field cannot be w ritten w hen the USART is enabled UEN 1 This bit is reserved in USART1 20 ABDEN Auto baud rate enable 0 Auto baud rate detection is disabled 1 Auto baud rate detection is enabled This bit is reserved in USART1 19 MSBF Most significant bit first 0 Data is transmitted received w ith the LSB first 1 Data is transmitted received w ...

Page 612: ...w value on CK pin outside transmission w indow in synchronous mode 1 Steady high value on CK pin outside transmission w indow in synchronous mode This bit field cannot be w ritten w hen the USART is enabled UEN 1 9 CPH Clock phase 0 The first clock transition is the first data capture edge in synchronous mode 1 The second clock transition is the first data capture edge in synchronous mode This bit...

Page 613: ...CTL2 Address offset 0x08 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved WUIE WUM 1 0 SCRTNUM 2 0 Reserved rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEP DEM DDRE OVRD OSB CTSIE CTSEN RTSEN DENT DENR SCEN NKEN HDEN IRLP IREN ERRIE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 23 Reser...

Page 614: ... transceiver control through the DE signal w hich is output on the RTS pin 0 DE function is disabled 1 DE function is enabled This bit field cannot be w ritten w hen the USART is enabled UEN 1 13 DDRE Disable DMA on reception error 0 DMA is not disabled in case of reception error The DMA request is not asserted to make sure the erroneous data is not transferred but the next correct received data w...

Page 615: ...w hen there is space in the receive buffer This bit field cannot be w ritten w hen the USART is enabled UEN 1 7 DENT DMA enable for transmission 0 DMA mode is disabled for transmission 1 DMA mode is enabled for transmission 6 DENR DMA enable for reception 0 DMA mode is disabled for reception 1 DMA mode is enabled for reception 5 SCEN Smartcard mode enable 0 Smartcard Mode disabled 1 Smartcard Mode...

Page 616: ... Reset value 0x0000 0000 This register has to be accessed by word 32 bit This register cannot be written when the USART is enabled UEN 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRR 15 4 BRR 3 0 rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 4 BRR 15 4 Integer of baud rate divider DIV_INT 11 0 BRR 15 4 3 0 BRR 3 0 ...

Page 617: ...divides the source clock by 2 In IrDA normal mode 00000001 can be set this value only In smartcard mode the prescaler value for dividing the system clock is stored in PSC 4 0 bits And the bits of PSC 7 5 must be kept at reset value The division factor is tw ice as the prescaler value 00000 Reserved do not program this value 00001 divides the source clock by 2 00010 divides the source clock by 4 00...

Page 618: ...ud clocks In standard mode the RTF flag is set if no new start bit is detected for more than the RT value after the last received character In smartcard mode the CWT and BWT are implemented by this value In this case the timeout measurement is started from the start bit of the last received character These bits can be w ritten on the fly The RTF flag w ill be set if the new value is low er than or...

Page 619: ...alue 0x0000 00C0 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved REA TEA WUF RWU SBF AMF BSY r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ABDF ABDE Reserved EBF RTF CTS CTSF LBDF TBE TC RBNE IDLEF ORERR NERR FERR PERR r r r r r r r r r r r r r r r Bits Fields Descriptions 31 23 Reserved Must be kept at reset value 22 REA Receive enabl...

Page 620: ...o break character is transmitted 1 Break character w ill be transmitted This bit indicates that a send break character w as requested Set by softw are by w riting 1 to the SBKCMD bit in the USART_CMD register Cleared by hardw are during the stop bit of break transmission 17 AMF ADDR match flag 0 ADDR does not match the received character 1 ADDR matches the received character An interrupt is genera...

Page 621: ...e w hen the RT value programmed in the USART_RT register has lapsed w ithout any communication Cleared by w riting 1 to RTC bit in USART_INTC register The timeout corresponds to the CWT or BWT timings in smartcard mode This bit is reserved in USART1 10 CTS CTS level This bit equals to the inverted level of the nCTS input pin 0 nCTS input pin is in high level 1 nCTS input pin is in low level 9 CTSF...

Page 622: ...the USART_RDATA Cleared by reading the USART_RDATA or w riting 1 to RXFCMD bit of the USART_CMD register 4 IDLEF IDLE line detected flag 0 No Idle Line is detected 1 Idle Line is detected An interrupt w ill occur if the IDLEIE bit is set in USART_CTL0 Set by hardw are w hen an Idle Line is detected It w ill not be set again until the RBNE bit has been set itself Cleared by w riting 1 to IDLEC bit ...

Page 623: ...it is set in USART_CTL0 Set by hardw are w hen a parity error occurs in receiver mode Cleared by w riting 1 to PEC bit in USART_INTC register 18 4 9 Interrupt status clear register USART_INTC Address offset 0x20 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved WUC Reserved AMC Reserved w w 15 14 13 12 11 10 9 8 7 6 5 4...

Page 624: ...clears the TC bit in the USART_STAT register 5 Reserved Must be kept at reset value 4 IDLEC Idle line detected clear Writing 1 to this bit clears the IDLEF bit in the USART_STAT register 3 OREC Overrun error clear Writing 1 to this bit clears the ORERR bit in the USART_STAT register 2 NEC Noise detected clear Writing 1 to this bit clears the NERR bit in the USART_STAT register 1 FEC Frame error fl...

Page 625: ...17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TDATA 8 0 rw Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 0 TDATA 8 0 Transmit Data value The transmit data character is contained in these bits The value w ritten in the MSB bit 7 or bit 8 depending on the data length w ill be replaced by the parity w hen transmitting w ith the parity is enabled PCEN bit set to ...

Page 626: ...it parity bit w hen pce is set has been sampled 18 4 13 USART receive FIFO control and status register USART_RFCS Address offset 0xD0 Reset value 0x0000 0400 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFFINT RFCNT 2 0 RFF RFE RFFIE RFEN Reserved ELNACK r_w0 r r r rw rw rw Bits Fields Descriptions 31...

Page 627: ...M 1 0 Receive FIFO disable 1 Receive FIFO enable 7 1 Reserved Must be kept at reset value 0 ELNACK Early NACK w hen smartcard mode is selected The NACK pulse occurs 1 16 bit time earlier w hen the parity error is detected 0 Early NACKdisable w hen smartcard mode is selected 1 Early NACKenable w hen smartcard mode is selected This bit is reserved in USART1 ...

Page 628: ...Parallel bus to I2C bus protocol converter and interface Both master and slave functions with the sameinterface Bi directional data transfer between master and slave Supports 7 bit and 10 bit addressing and general call addressing Multiple 7 bit slave addresses 2 address 1 with configurable mask Programmable setup time and hold time Multi master capability Supports standard mode up to 100 kHz and ...

Page 629: ...s Master the device w hich initiates a transfer generates clock signals and terminates a transfer Slave the device addressed by a master Multi master more than one master can attempt to control the bus at the same time w ithout corrupting the message Arbitration procedure to ensure that if more than one master tries to control the bus simultaneously only one is allow ed to do so and the w inning m...

Page 630: ...rora slave thus there re 4 operation modes for an I2C device Slave transmitter Slave receiver Master transmitter Master receiver Data validation The data on the SDA line must be stable during the HIGH period of the clock The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW seeFigure19 2 Datavalidation Oneclock pulseis generatedforeachdatabit transferr...

Page 631: ...nabled by software the I2C slave always responses to a General Call Address 0x00 The I2C block support both 7 bit and 10 bit address modes Data and addresses are transferred as 8 bit bytes MSB first The first byte s following the START condition contain the address one in 7 bit mode two in 10 bit mode The address is always transmitted in master mode A 9th clock pulse follows the 8 clock cycles of ...

Page 632: ...bit address Master Receive when HEAD10R 0 In 10 bit addressing mode if the master reception follows a master transmission between the same master and slave the address read sequence can be RESTART header of 10 bit address in read direction as is shown in Figure 19 8 I2C communication flow with 10 bit address Master Receive when HEAD10R 1 Figure 19 7 I2C communication flow with 10 bit address Maste...

Page 633: ...of the SCL or the SDA line is internally changed only if it remains stable for more than DNF 3 0 x tI2CCLK This allows to suppress spikes with a programmable length of 1 to 15 of tI2CCLK 19 3 4 I2C timings The PSC 3 0 SCLDELY 3 0 and SDADELY 3 0 bits in the I2C_TIMING register must be configured in order to guarantee a correct data hold and setup time used in I2C communication If the data is alrea...

Page 634: ...than the maximum of tVD DAT When SS 0 after tSDADELY delay the slave had to stretch the clock before the data writing to I2C_TDATA register SCL is low during the data setup time The setup time is tSCLDELY SCLDELY 1 tPSC tSCLDELY effects tSU DAT SCLDELY must match condition as follows SCLDELY tr max tSUDAT min PSC 1 tI2CCLK 1 In master mode the SCL clock high and low levels must be configured by pr...

Page 635: ...er bits are START STOP NACKEN in I2C_CTL1 register I2CBSY TBE TI RBNE ADDSEND NACK TCR TC STPDET BERR LOST ARB and OUERR in I2C_STAT register Additionally when the SMBus is supported PECTRANS in I2C_CTL1 register PECERR TIMEOUT and SMBALT in I2C_STAT are also impacted In order to perform the software reset I2CEN must be kept low during at least 3 APB clock cycles This is ensured by writingsoftware...

Page 636: ...2C_RDATA register If RBNE 1 indicates that the previous received data byte has not been read the SCLline is stretched low until I2C_RDATA is read The stretch is inserted between the 8th and 9th SCL pulse beforeAcknowledgepulse Figure 19 12 Data reception I2C_RDATA SCL Shift register xx data1 xx data2 xx RBNE data0 data1 data2 ACK pulse ACK pulse read data0 read data1 SCL Stretch Hardware transfer ...

Page 637: ...en to a non zero value TCR is cleared by software When the BYTENUM counter is reloaded with the last number of bytes RELOAD bit must be cleared When RELOAD 0 in master mode the counter canbe used in two modes Automatic end mode AUTOEND 1 in theI2C_CTL1 register In this mode once the number of bytes programmed in the BYTENUM 7 0 bit field has been transferred the master automatically sends a STOP c...

Page 638: ...ddress And TR bit in I2C_STAT register updates after the ADDSEND is set The bit will let the slave to know whether to act as a transmitter or receiver SCL line stretching The clock stretching is used in slave mode by default SS 0 the SCL line can be stretched low if necessary The SCL will be stretched in following cases The SCL is stretched when theADDSEND bit is set and released when theADDSEND b...

Page 639: ...slave byte control mode is not allowed When using slave byte control mode the reload mode must be enabled by setting the RELOAD bit in I2C_CTL1 register In order to get control of each byte BYTENUM 7 0 in I2C_CTL1 register must be configured as 1 in the ADDSEND interrupt service routine and reloaded to 1 after each byte received The TCR bit in I2C_STAT register will be set when a byte is received ...

Page 640: ...t an interrupt will be generated The NACK bit in I2C_STAT register will be set when a NACK is received And an interrupt is generated if the NACKIE bit is set in the I2C_CTL0 register The TI bit in I2C_STAT register will not be set when a NACK is received The STPDET bit in I2C_STAT register will be set when a STOP is received If the STPDETIE in I2C_CTL0 register is set an interrupt will be generate...

Page 641: ...ave transmitter if a TI event is needed in order to generate a TI event both the TI bit and the TBE bit must be set Figure 19 14 Programming model for slave transmitting when SS 0 IDLE Master generates START condition Master sends Address Slave sends Acknowledge SCL stretched by slave Slave sends DATA 2 Master sends Acknowledge Data transmission Slave sends DATA N 1 Master sends Acknowledge Slave ...

Page 642: ...to I2C_TDATA Set TI Write DATA 3 to I2C_TDATA Write DATA 4 to I2C_TDATA Write DATA N to I2C_TDATA Set TI I2C Line State Hardware Action Software Flow Slave sends DATA 1 Master sends Acknowledge Write DATA N 1 to I2C_TDATA DATA N 1 will not be sent Clear STPDET Write DATA 1 to I2C_TDATA Set TI Slave sends DATA N Master don t send ACK Set TI TBE and NACK Clear NACK Set TBE Slave receiver When the I2...

Page 643: ...a clock synchronization mechanism is implemented For clock synchronization the low level of the clock is counted starting from the SCL low level internal detection by the SCLL 7 0 counter the high level of the clock is counted by the SCLH 7 0 counter starting from the SCL high level internal detection The I2C detects its SCLlow level after a tSYNC1 delay depending on the SCLfalling edge SCL input ...

Page 644: ...55 BYTENUM 7 0 should be configured as 0xFF Then the master sends the START condition All the bits above should be configured before the START is set The slave address will be sent after the START condition when the I2CBSY bit I2C_STAT register is detected as 0 When the arbitration is lost the master changes to slave mode and the START bit will be cleared by hardware When the slave address has bee...

Page 645: ... STOP bit in the I2C_CTL1 register Or generate a RESTART condition to start a new transfer The TC bit is cleared when the START STOP bit is set If a NACK is received a STOP condition is automatically generated the NACK is set in I2C_STAT register if the NACKIE bit is set an interrupt will be generated Note When the RELOAD bit is 1 theAUTOEND has no effect Figure 19 18 Programming model for master ...

Page 646: ...TA Set TI Write DATA 2 to I2C_TDATA Write DATA 3 to I2C_TDATA Write DATA N to I2C_TDATA Master sends DATA N 1 Slave sends Acknowledge Set TI Master sends DATA N Slave sends Acknowledge Set TC Master receiver In master receiving mode the RBNE bit in I2C_STAT register will be set when a byte is received If the RBNEIE bit is set in I2C_CTL0 register an interrupt will be generated If the number of byt...

Page 647: ...TA 1 Master sends Acknowledge Data transmission Slave sends DATA N Master don t send ACK Master generates STOP condition Software initialization Set RBNE Set RBNE Read DATA x Set RBNE Read DATA 1 Slave sends DATA N 1 Master sends Acknowledge Set RBNE Read DATA N set STOP I2C Line State Hardware Action Software Flow Set START Read DATA N 1 AUTOEND 0 BYTENUM 7 0 N ...

Page 648: ...Slave sends DATA N Master sends Acknowledge Set RBNE Set RBNE TC Read DATA x Set RBNE Read DATA 1 Slave sends DATA N 1 Master sends Acknowledge Set RBNE Read DATA N Read DATA N 1 Set STOP 19 3 9 SMBus support The System Management Bus abbreviated to SMBus or SMB is a single ended simple two wire bus for thepurposeof lightweight communication Mostcommonlyit is foundincomputer motherboards for commu...

Page 649: ... slave mode the Slave Byte Control mode must be enabled by setting SBCTL bit in I2C_CTL0 register Host Notify protocol When the SMBHAEN bit in the I2C_CTL0 register is set the SMBus supports the Host Notify protocol Thehost will acknowledgetheSMBus Hostaddress Whenthisprotocol is used the device acts as a master and the host as a slave Time out feature SMBus has a time out feature which resets dev...

Page 650: ...ulator in I2C block to perform Packet Error Checking for I2C data A PEC packet error code byte is appended at the end of each transfer The byte is calculated as CRC 8 checksum calculatedovertheentiremessageincludingtheaddress andread write bit The polynomial used is x8 x2 x 1 the CRC 8 ATM HEC algorithm initialized to zero Setting the PECEN bit in the I2C_CTL0 register will enable the PEC calculat...

Page 651: ...s idle detection The BUSTOA 11 0 bits must be programmed with the timer reload value to enable the tIDLE check in order to obtain the tIDLE parameter To detect SCL and SDA high level timeouts the TOIDLE bit must be set Then set TOEN in the I2C_TIMEOUT register to enable the timer If the high level time of both SCL and SDA is greater than BUSTOA 1 x 4 x tI2CCLK the TIMEOUT flag is set in the I2C_ST...

Page 652: ...trol is not required then PECTRANS can be set to 1 and BYTENUM can be programmed according to thenumber of bytes to be received Note After the RELOAD bit is set thePECTRANS cannot be changed Figure 19 22 SMBusMaster Transmitter and Slave Receiver communication flow Start Slave address ACK DATA0 ACK DATA N 1 ACK Stop data transfer N 1 bytes From master to slave From slave to master W 0 PEC ACK SMBu...

Page 653: ... MCU will not be wake up Only an address match interrupt ADDMIE 1 can wakeup the MCU If the clock source of I2C is thesystem clock orWUEN 0 IRC16M will not switchedonafterreceivingstart signal When wakeup from Deep sleep mode is enabled the digital filter must be disabled and the SS bit in I2C_CTL0 must be cleared Before entering Deep sleep mode I2CEN 0 the I2C peripheral must be disabled if wakeu...

Page 654: ...rupt event Event flag Enable control bit I2C_RDATA is not empty during receiving RBNE RBNEIE Transmit interrupt TI TIE STOP condition detected in slave mode STPDET STPDETIE Transfer complete reload TCR TCIE Transfer complete TC Address match ADDSEND ADDMIE Not acknow ledge received NACK NACKIE Bus error BERR ERRIE Arbitration Lost LOSTARB Overrun Underrun error OUERR PEC error PECERR Timeout error...

Page 655: ...TCIE STPDETI E NACKIE ADDMIE RBNEIE TIE I2CEN rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 PECEN PEC Calculation Sw itch 0 PEC Calculation off 1 PEC Calculation on 22 SMBALTEN SMBus Alert enable 0 SMBA pin is not pulled dow n device mode or SMBus Alert pin SMBA is disabled host mode 1 SMBA pin is pulled dow n device mode or SMBus Alert ...

Page 656: ... control is disabled 1 Slave byte control is enabled 15 DENR DMA enable for reception 0 DMA is disabled for reception 1 DMA is enabled for reception 14 DENT DMA enable for transmission 0 DMA is disabled for transmission 1 DMA is enabled for transmission 13 Reserved Must be kept at reset value 12 ANOFF Analog noise filter disable 0 Analog noise filter is enabled 1 Analog noise filter is disabled No...

Page 657: ...3 ADDMIE Address match interrupt enable in slave mode 0 Address match ADDSEND interrupt is disabled 1 Address match ADDSEND interrupt is enabled 2 RBNEIE Receive interrupt enable 0 Receive RBNE interrupt is disabled 1 Receive RBNE interrupt is enabled 1 TIE Transmit interrupt enable 0 Transmit TI interrupt is disabled 1 Transmit TI interrupt is enabled 0 I2CEN I2C peripheral enable 0 I2C is disabl...

Page 658: ...es have been transferred the TCR bit in I2C_STAT register w illbe set This bit is set and cleared by softw are 23 16 BYTENUM 7 0 Number of bytes to be transferred These bits are programmed w ith the number of bytes to be transferred When SBCTL 0 these bits have no effect Note These bits should not be modified w hen the START bit is set 15 NACKEN Generate NACK in slave mode 0 an ACK is sent after r...

Page 659: ... this bit can not be modified 10 TRDIR Transfer direction in master mode 0 Master transmit 1 Master receive Note When the START bit is set this bit can not be modified 9 0 SADDRESS 9 0 Slave address to be sent SADDRESS 9 8 Slave address bit 9 8 If ADD10EN 0 these bits have no effect If ADD10EN 1 these bits should be w ritten w ith bits 9 8 of the slave address to be sent SADDRESS 7 1 Slave address...

Page 660: ... 9 8 Highest tw o bits of a 10 bit address Note When ADDRESSEN is set this bit should not be w ritten 7 1 ADDRESS 7 1 7 bit address or bits 7 1 of a 10 bit address Note When ADDRESSEN is set this bit should not be w ritten 0 ADDRESS0 Bit 0 of a 10 bit address Note When ADDRESSEN is set this bit should not be w ritten 19 4 4 Slave address register 1 I2C_SADDR1 Address offset 0x0C Reset value 0x0000...

Page 661: ...s 0b0000xxx and 0b1111xxx are not acknow ledged even if all the bits are matched 7 1 ADDRESS2 7 1 Second I2C address for the slave Note When ADDRESS2EN is set these bits should not be w ritten 0 Reserved Must be kept at reset value 19 4 5 Timing register I2C_TIMING Address offset 0x10 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ...

Page 662: ...0 SCLL 7 0 SCL low period SCL low period can be generated by configuring these bits tSCLL SCLL 1 x tPSC Note These bits can only be used in master mode 19 4 6 Timeout register I2C_TIMEOUT Address offset 0x14 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EXTOEN Reserved BUSTOB 11 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOE...

Page 663: ...the bus is idle Note This bit can be w ritten only w hen TOEN 0 11 0 BUSTOA Bus timeout A When TOIDLE 0 tTIMEOUT BUSTOA 1 x 2048 x tI2CCLK When TOIDLE 1 tIDLE BUSTOA 1 x 4 x tI2CCLK Note These bits can be w ritten only w hen TOEN 0 19 4 7 Status register I2C_STAT Address offset 0x18 Reset value 0x0000 0001 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 664: ...red by softw are by setting the TIMEOUTC bit and cleared by hardw are w hen I2CEN 0 0 no timeout or extended clock timeout occur 1 a timeout or extended clock timeout occur 11 PECERR PEC error This flag is set by hardw are w hen the received PEC does not match w ith the content of I2C_PEC register Then a NACK is automatically sent It is cleared by softw are by setting the PECERRC bit and cleared b...

Page 665: ...fer of BYTENUM 7 0 bytes is completed 5 STPDET STOP condition detected in slave mode This flag is set by hardw are w hen a STOP condition is detected on the bus It is cleared by softw are by setting STPDETC bit and cleared by hardw are w hen I2CEN 0 0 STOP condition is not detected 1 STOP condition is detected 4 NACK Not Acknow ledge flag This flag is set by hardw are w hen a NACK is received It i...

Page 666: ...DATA register 0 I2C_TDATA is not empty 1 I2C_TDATA is empty 19 4 8 Status clear register I2C_STATC Address offset 0x1C Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SMBALT C TIMEOUT C PECERR C OUERRC LOSTAR BC BERRC Reserved STPDET C NACKC ADDSEN DC Reserved w w w w w w w ...

Page 667: ...SEND bit of I2C_STAT by w rite 1 to this bit 2 0 Reserved Must be kept at reset value 19 4 9 PEC register I2C_PEC Address offset 0x20 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PECV 7 0 r Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 PECV 7 0 Pa...

Page 668: ... by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TDATA 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 TDATA 7 0 Transmit data value 19 4 12 Control register 2 I2C_CTL2 Address offset 0x90 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 669: ...h bits of ADDRESS 7 1 are compared w ith an incoming address byte and w hich bits are ignored Any bit set to 1 in ADDM 6 0 enables comparisons w ith the corresponding bit in ADDRESS 7 1 Bits set to 0 are ignored can be either 0 or 1 in the incoming address 8 0 Reserved Must be kept at reset value ...

Page 670: ...realized in I2S1 20 2 Characteristics 20 2 1 SPI characteristics Master or slave operation with full duplex or simplex mode Separate transmit and receive buffer 16 bits wide Data frame size can be 8 or 16 bits Bit order can be LSB or MSB Software and hardware NSS management Hardware CRC calculation transmission and checking Transmission and reception using DMA SPI TI mode supported Quad SPI config...

Page 671: ...nal description Pin name Direction Description SCK I O Master SPI clock output Slave SPI clock input MISO I O Master Data reception line Slave Data transmission line Master w ith bidirectional mode Not used Slave w ith bidirectional mode Data transmission and reception line MOSI I O Master Data transmission line Slave Data reception line Master w ith bidirectional mode Data transmission and recept...

Page 672: ... The SPI is connected to external devices through 6 pins in Quad SPI mode Table 20 2 Quad SPI signal description Pin name Direction Description SCK O SPI clock output MOSI I O Transmission Reception data 0 MISO I O Transmission Reception data 1 IO2 I O Transmission Reception data 2 IO3 I O Transmission Reception data 3 NSS O NSS output 20 5 SPI function overview 20 5 1 SPI clock timing and data fo...

Page 673: ...D 0 D 1 D 2 D 3 SCK MOSI MISO IO2 IO3 NSS sample In normal mode the length of data is configured by the FF16 bit in the SPI_CTL0 register Data length is 16 bits if FF16 1 otherwise is 8 bits The data frame length is fixedto 8 bits in Quad SPI mode Data order is configured by the LF bit in SPI_CTL0 register and SPI will first send the LSB first if LF 1 or the MSB first if LF 0 The data order is fix...

Page 674: ...fter SPI is enabled and goes low whentransmission orreceptionprocess begins WhenSPIis disabled theNSS goes high The application may also use a general purpose IO as NSS pin to realize more flexible NSS 20 5 3 SPI operating modes Table 20 3 SPI operating modes Mode Description Register configuration Data pin usage MFD Master full duplex MSTMOD 1 RO 0 BDEN 0 BDOEN Don t care MOSI Transmission MISO R...

Page 675: ...onal connection MSTMOD 0 RO 1 BDEN 0 BDOEN Don t care MOSI Reception MISO Not used STB Slave transmission w ith bidirectional connection MSTMOD 0 RO 0 BDEN 1 BDOEN 1 MOSI Not used MISO Transmission SRB Slave reception w ith bidirectional connection MSTMOD 0 RO 0 BDEN 1 BDOEN 0 MOSI Not used MISO Reception Figure 20 4 A typical full duplex connection Master MFD MISO MOSI SCK NSS Slave SFD MISO MOSI...

Page 676: ...re the Td time in TI mode otherwise ignore this step 2 Program data format FF16 bit in the SPI_CTL0 register 3 Program the clock timing register CKPL and CKPH bits in the SPI_CTL0 register 4 Program the frame format LF bit in the SPI_CTL0 register 5 Program the NSS mode SWNSSEN and NSSDRV bits in the SPI_CTL0 register according to the application s demand as described above in NSS function section...

Page 677: ...ter the last valid sample clock the incoming data will be moved from shift register to the receive buffer and RBNE receive buffer not empty will be set The application should read SPI_DATA register to get the received data and this will clear the RBNE flag automatically In MRU and MRB modes hardware continuously sends clock signal to receive the next data frame while in full duplex master mode MFD...

Page 678: ... D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCK NSS MOSI MISO sample Figure 20 9 Timing diagram of TI master mode with continuoustransfer D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCK NSS MOSI MISO sample In master TI mode SPI can perform continuous or non continuous transfer If the master writes SPI_DATA register fast enough the tra...

Page 679: ...toggles at the middlebit of a byte Quad SPI mode operation sequence The Quad SPI mode is designed to control Quad SPI flash In order to enter Quad SPI mode the software should first verify that the TBE bit is set and TRANS bit is cleared then set QMOD bit in SPI_QCTL register In Quad SPI mode BDEN BDOEN CRCEN CRCNT FF16 RO and LF bits in SPI_CTL0 register should be kept cleared and MSTMOD should b...

Page 680: ...uad read mode when QMOD and QRD bits are both set in SPI_QCTL register In this mode MOSI MISO IO2 and IO3 are all used as input pins SPI begins to generate clock on SCK line as soon as a data is written into SPI_DATA TBE is cleared and SPIEN is set Writing data into SPI_DATA is only to generate SCK clocks so the written data can be any value Once SPI starts transmission it always checks SPIEN and ...

Page 681: ...I in different operation modes MFD SFD Wait forthelast RBNE flagandthenreceive thelast data Confirm that TBE 1andTRANS 0 At last disable the SPI by clearing SPIEN bit MTU MTB STU STB Write the last data into SPI_DATA and wait until the TBE flag is set and then wait until the TRANS flag is cleared Disable the SPI by clearing SPIEN bit MRU MRB After getting the second last RBNE flag read out this da...

Page 682: ... data into the SPI_DATA register automatically If DMAREN is set SPI will generate a DMA request each time when RBNE 1 then DMA will acknowledge to this request and read data from the SPI_DATA register automatically 20 5 5 CRC function There are two CRC calculators in SPI one for transmission and the other for reception The CRC calculation uses the polynomial defined in SPI_CRCPOLY register Applica...

Page 683: ...he NSSDRV is not enabled the CONFERR is set when the NSS pin is pulled low In NSS software mode the CONFERR is set when the SWNSS bit is 0 When the CONFERR is set the SPIEN bit and the MSTMOD bit are cleared by hardware the SPI is disabled and the device is forced into slave mode The SPIEN and MSTMOD bits are write protected until the CONFERR is cleared The CONFERR bit of the slave cannot be set I...

Page 684: ...Block diagram of I2S Clock Generator SPI_MOSI I2S_SD SPI_NSS I2S_WS SPI_SCK I2S_CK I2S_MCK Master Control Logic Slave Control Logic TX Buffer Shift Register RX Buffer Control Registers 16 bits CK_I2S 16 bits LSB MSB PAD PAD O I O I PAD O I PAD O I APB There are five sub modules to support I2S function including control registers clock generator master control logic slave control logic and shift re...

Page 685: ...re configured by the DTLEN bits and CHLEN bit in the SPI_I2SCTL register Since the channel length must be greater than or equal to the data length four packet types are available They are 16 bit data packed in 16 bit frame 16 bit data packed in 32 bit frame 24 bit data packed in32 bit frame and 32 bit data packed in 32 bit frame The data buffer for transmission and reception is 16 bit wide In the ...

Page 686: ... MSB LSB I2S_WS Figure 20 17 I2S Phillipsstandard timing diagram DTLEN 10 CHLEN 1 CKPL 1 I2S_CK I2S_SD 32 bit data frame 1 channel left frame 2 channel right MSB MSB LSB I2S_WS When the packet type is 32 bit data packed in 32 bit frame two write or read operations to or from the SPI_DATA register are needed to complete the transmission of a frame In transmission mode if a 32 bit data is going to b...

Page 687: ...e lower 8 bits are zeros Figure 20 20 I2S Phillipsstandard timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB Figure 20 21 I2S Phillipsstandard timing diagram DTLEN 00 CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB When the packet type is 16 bit data...

Page 688: ...LEN 1 CKPL 1 I2S_CK I2S_SD 32 bit data frame 1 channel left frame 2 channel right MSB MSB LSB I2S_WS Figure 20 26 MSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 0 I2S_CK I2S_SD 24 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 8 bit 0 MSB Figure 20 27 MSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 24 bit data frame 1 channel left frame ...

Page 689: ...ght I2S_WS 24 bit data MSB LSB Figure 20 31 LSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 8 bit 0 frame 1 channel left frame 2 channel right I2S_WS 24 bit data MSB LSB When the packet type is 24 bit data packed in 32 bit frame two write or read operations to or from the SPI_DATA register are needed to complete the transmission of a frame In transmission mode if a 24 b...

Page 690: ...nd the long frame synchronization mode are available and configurable using the PCMSMOD bit in the SPI_I2SCTL register The SPI_DATA register is handled in the exactly same way as that for I2S Phillips standard The timing diagrams for each configuration of the short frame synchronization mode are shown below Figure 20 34 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 0 ...

Page 691: ... 1 CKPL 1 I2S_CK I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 8 bit 0 Figure 20 40 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 16 bit 0 Figure 20 41 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 16 bit...

Page 692: ...L 0 I2S_CK I2S_SD 32 bits MSB I2S_WS MSB LSB frame 1 frame 2 13 bits Figure 20 45 PCM standard long frame synchronization mode timing diagram DTLEN 10 CHLEN 1 CKPL 1 I2S_CK I2S_SD 32 bits MSB I2S_WS MSB LSB frame 1 frame 2 13 bits Figure 20 46 PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 0 I2S_CK I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 13 bits 8 bit 0...

Page 693: ...2 1 0 CHLEN 0 1 MCKOEN I2S_CK I2S_MCK The block diagram of I2S clock generator is shown as Figure 20 50 Block diagram of I2S clock generator The I2S interface clocks are configured by the DIV bits the OF bit the MCKOEN bit in the SPI_I2SPSC register and the CHLEN bit in the SPI_I2SCTL register The I2S bitrate can be calculated by the formulas shown in Table 20 5 I2S bitrate calculation formulas Ta...

Page 694: ... for each operation mode Table 20 7 Direction of I2S interface signalsfor each operation mode Operation mode I2S_MCK I2S_CK I2S_WS I2S_SD I2S_ADD_SD 2 Master transmission output or NU 1 output output output NU 1 Master reception output or NU 1 output output input NU 1 Slave transmission input or NU 1 input input output NU 1 Slave reception input or NU 1 input input input NU 1 Full duplex output or...

Page 695: ...buffer to the shift register TBE goes high immediately At the moment the transmission sequence begins The data is parallel loaded into the 16 bit shift register and shifted out serially to the I2S_SD pin MSB first The next data should be written to the SPI_DATA register when the TBE flag is high After a write operation to the SPI_DATA register the TBE flag goes low When the current transmission fi...

Page 696: ...Then wait 17 I2S CK clock clock on I2S_CK pin cycles 3 Clear the I2SEN bit 16 bit data packed in 32 bit frame in the audio standards except the LSB justified standard DTLEN 00 CHLEN 1 and I2SSTD is not equal to 0b10 1 Wait for the last RBNE 2 Then wait one I2S clock cycle 3 Clear the I2SEN bit For all other cases 1 Wait for the second last RBNE 2 Then wait one I2S clock cycle 3 Clear the I2SEN bit...

Page 697: ...2S module but can only work in slave mode There is only one I2S_ADD1 module so only I2S1 supports full duplex mode I2S_ADD s I2S_CK and I2S_WS are internally connected to its respective I2S s respective ports I2S_ADD s I2S_SD pin is mapped to respective I2S s SPI_MISOpin In order to work in full duplex mode application should enable the I2S module as well as its correspondingI2S_ADDmodule I2S supp...

Page 698: ...e This flag will not generate any interrupt I2S channel side flag I2SCH This flag indicates the channel side information of the current transfer and has no meaning in PCM mode It is updated when TBE rises in transmission mode or RBNE rises in reception mode This flag will not generate any interrupt 20 10 2 Error flags There are three error flags Transmission underrun error flag TXURERR This situat...

Page 699: ...TBE Transmit buffer empty Write SPI_DATA register TBEIE RBNE Receive buffer not empty Read SPI_DATA register RBNEIE TXURERR Transmission underrun error Read SPI_STAT register ERRIE RXORERR Reception overrun error Read SPI_DATA register and then read SPI_STAT register FERR I2S format error Read SPI_STAT register ...

Page 700: ...17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BDEN BDOEN CRCEN CRCNT FF16 RO SWNSS EN SWNSS LF SPIEN PSC 2 0 MSTMOD CKPL CKPH rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 BDEN Bidirectional enable 0 2 line unidirectional transmit mode 1 1 line bidirectional transmit mode The information transfers betw een the MOSI pin in ma...

Page 701: ...e mode The NSS level depends on SWNSS bit This bit has no meaning in SPI TI mode 8 SWNSS NSS pin selection in NSS softw are mode 0 NSS pin is pulled low 1 NSS pin is pulled high This bit effects only w hen the SWNSSEN bit is set This bit has no meaning in SPI TI mode 7 LF LSB first mode 0 Transmit MSB first 1 Transmit LSB first This bit has no meaning in SPI TI mode 6 SPIEN SPI enable 0 SPI periph...

Page 702: ... enabled An interrupt is generated w hen the TBE bit is set 6 RBNEIE Receive buffer not empty interrupt enable 0 RBNE interrupt is disabled 1 RBNE interrupt is enabled An interrupt is generated w hen the RBNE bit is set 5 ERRIE Errors interrupt enable 0 Error interrupt is disabled 1 Error interrupt is enabled An interrupt is generated w hen the CRCERR bit the CONFERR bit the RXORERR bit or the TXU...

Page 703: ... 5 4 3 2 1 0 Reserved FERR TRANS RXORERR CONFERR CRCERR TXURERR I2SCH TBE RBNE rc_w0 r r r rc_w0 r r r r Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 FERR Format error SPI TI Mode 0 No TI mode format error 1 TI mode format error occurs I2S Mode 0 No I2S format error 1 I2S format error occurs This bit is set by hardw are and cleared by w riting 0 7 TRANS Transmitting ongoing...

Page 704: ...Transmission underrun error occurs This bit is set by hardw are and cleared by a read operation on the SPI_STAT register This bit is not used in SPI mode 2 I2SCH I2S channel side 0 The next data needs to be transmitted or the data just received is channel left 1 The next data needs to be transmitted or the data just received is channel right This bit is set and cleared by hardw are This bit is not...

Page 705: ...sion and reception transmit buffer and receive buffer are 16 bit 20 11 5 CRC polynomial register SPI_CRCPOLY Address offset 0x10 Reset value 0x0000 0007 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRCPOLY 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 ...

Page 706: ...eset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCRC 15 0 r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 TCRC 15 0 TX CRC value When the CRCEN bit of SPI_CTL0 is set the hardw are computes the CRC value of the transmitted bytes and saves...

Page 707: ...configured w hen SPI I2S is disabled 10 I2SEN I2S enable 0 I2S is disabled 1 I2S is enabled This bit is not used in SPI mode 9 8 I2SOPMOD 1 0 I2S operation mode 00 Slave transmission mode 01 Slave reception mode 10 Master transmission mode 11 Master reception mode This bit should be configured w hen I2S is disabled This bit is not used in SPI mode 7 PCMSMOD PCM frame synchronization mode 0 Short f...

Page 708: ...d in SPI mode 0 CHLEN Channel length 0 16 bits 1 32 bits The channel length must be equal to or greater than the data length This bit should be configured w hen I2S mode is disabled This bit is not used in SPI mode 20 11 9 I2S clock prescaler register SPI_I2SPSC Address offset 0x20 Reset value 0x0000 0002 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 2...

Page 709: ...2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IO23_DR V QRD QMOD rw rw rw Bits Fields Descriptions 31 3 Reserved Must be kept at reset value 2 IO23_DRV Drive IO2 and IO3 enable 0 IO2 and IO3 are not driven in single w ire mode 1 IO2 and IO3 are driven to high in single w ire mode This bit is only available in SPI0 1 QRD Quad SPI mode ...

Page 710: ...GD32W51x User Manual 710 ...

Page 711: ...is divided by HCLK SQPI controller support no address phase and data phase operation whichis named special command by the controller SQPI controller support READ ID command which is more than 32 bit data during one AHB command SQPI controller support AHB burst operation and 8 16 32 bitAHB command SQPI controller support 256MB external memory space Logic memory address range 0x6000_0000 0x6FFF_FFFF...

Page 712: ...O IO IO SQPI_D2 Inout X IO IO IO X X SQPI_D3 Inout X IO IO IO X X Note O Output I Input IO Inout 0 Output 0 1 Output 1 X Hiz 21 3 2 SQPI controller sampling polarity SQPI controller read operation sampling polarity PL bit in SQPI_INIT register selection function support user to change the controller sampling time This function is highly useful when SQPI clock is high Example showed as below Figure...

Page 713: ... SQPI SCMD Example SQPI_D0 SQPI_D1 SQPI_CLK SQPI_CSN SQPI_D2 SQPI_D3 Command Phase 7 0 21 3 4 SQPI controller read ID command For more than 32 bit ID data RDID function can supply help To use this function first you should set IDLEN bit SQPI_INIT register to 0x00 64bit this is default then set the RDID SQPI_RCMD register bit to 1 and wait it cleared by hardware through polling this bit and at last...

Page 714: ... is configured by CLKDIV bits 21 3 7 Read ID command flow The first usershouldconfigureRCMDbits by ReadID command e g 0x9F forSQPIPSRAM and read waitcycle number in SQPI_RCMD register The second user sets RID bit to 1 and wait it reset to 0 The third user can get ID value by read SQPI_IDL and SQPI_IDH registers 21 3 8 Read Write operation flow Six modes of memory access are possible Access mode sh...

Page 715: ...e Timing SQPI_D0 SQPI_D1 SQPI_CLK SQPI_CSN SQPI_D2 SQPI_D3 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 23 Command Phase Address Phase Data Phase Waitcycle Phase 7 0 Byte0 Byte1 Figure 21 7 SQPI SQQ Mode Timing SQPI SQPI_D0 SQPI_D1 SQPI_CLK SQPI_CSN SQPI_D2 SQPI_D3 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Command Phase Address Phase Data Phase Waitcycle Ph...

Page 716: ...e0 Byte1 Figure 21 9 SQPI SSD Mode Timing SQPI_D0 SQPI_D1 SQPI_CLK SQPI_CSN SQPI_D2 SQPI_D3 0 0 1 2 3 4 5 6 7 23 Command Phase Address Phase Data Phase Waitcycle Phase 7 0 Byte0 Figure 21 10 SQPI SDD Mode Timing SQPI_D0 SQPI_D1 SQPI_CLK SQPI_CSN SQPI_D2 SQPI_D3 0 1 0 1 2 3 4 5 6 7 19 18 20 21 22 23 Command Phase Address Phase Data Phase Waitcycle Phase 7 0 Byte0 21 4 Register definition SQPI secur...

Page 717: ...g edge 30 29 IDLEN 1 0 SQPI controller external memory ID length 00 64 bit 01 32 bit 10 16 bit 11 8 bit 28 24 ADDRBIT 4 0 Bit number of SPI PSRAM address phase Default 24 23 18 CLKDIV 5 0 Clock divider for SQPI output clock 0x0 is invalid Output clock frequency is fhclk CLKDIV 1 Note When CLKDIV field is even number the output clock high level time has 1 HCLK period more than low level time 17 16 ...

Page 718: ... command w aitcycle number after address phase 15 0 RCMD 15 0 SQPI read command for AHB read transfer RCMD 3 0 are valid w hen CMDBIT 00 RCMD 7 0 are valid w hen CMDBIT 01 RCMD 15 0 are valid w hen CMDBIT 10 NOTE Before write 1 to RID bit you must ensureit is cleared and after setRID to 1 you mustwaitRID cleared 21 4 3 SQPI Write Command Register SQPI_WCMD Address offset 0x08 Reset value 0x0001 00...

Page 719: ...ared and after set SC to 1 you must wait SC cleared 21 4 4 SQPI ID Low Register SQPI_IDL Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDL 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDL 15 0 r Bits Fields Descriptions 31 0 IDL 31 0 ID Low Data saved for SQPI Read ID Command IDL 15 0 is valid w hen IDLE...

Page 720: ...2W51x User Manual 720 IDH 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDH 15 0 r Bits Fields Descriptions 31 0 IDH 31 0 ID High Data saved for SQPI read ID command This register only valid w hen IDLEN 00 ...

Page 721: ...ogrammable command format for both indirect and memory mapped mode Integrated FIFO for transmission reception 8 16 or 32 bit data accesses DMA channel for indirect mode Interrupt generation on FIFO threshold status match timeout transfer complete and access error Support TrustZone architecture to isolate the secure area and non secure area 22 3 Function overview 22 3 1 QSPI block diagram Module QS...

Page 722: ...e data intput or output IO2 I O single mode connect WP pin of flash control w rite protect function dual mode connect WP pin of flash control w rite protect function qual mode data intput or output IO3 I O single mode connect HOLD pin of flash control hold function dual mode connect HOLD pin of flash control hold function qual mode data intput or output Figure 22 1 QSPI diagramshows the block diag...

Page 723: ...ion configured in INSTRUCTION field QSPI_TCFG register is sent to the flash memory IMOD field QSPI_TCFG register defines the instruction phase mode no instruction 1 line 2 lines or 4 lines Address phase In this phase 1 4 bytes of address are sent to theflash memory In Indirect mode ADDR field QSPI_ADDR register defines the information of address ADDRSZ field QSPI_TCFG register defines the number o...

Page 724: ...ad operation received data is obtained by reading DATA register In memory mapped mode the number of bytes to be transmitted is specified as single AHB bus access operation these could be 8 16 or 32 read write access corresponding to 1 2 or 4 bytes Also when the TZEN is set QSPI in memory mapped mode will check that if the haddr with the CPU secure status is an accessable transfer If not qspi will ...

Page 725: ...0 IO1 are alw ays high impedance In dummy phase w hen DATAMOD 2 b11 IO0 IO1 IO2 IO3 are alw ays high impedance IO2 IO3 are used only in quad mode if none of the 5 phases are configured in quad mode then IO2 IO3 are released and can be used for other functions even when QSPI is enabled 22 3 4 CSN and SCK behavior The default value of CSN is high and it falls before a command begins and rises as soo...

Page 726: ...each as specified by FMSZ If both DTLEN 0xFFFF_FFFF and FMSZ 0x1F then thetransmission continues indefinitely until the QSPI is disabled Transfer complete flag TC is set when the number of byte programed in DTLEN is reached in caseofundefined transferlength TC is set when thetransmit receivedbytenumberequals to external memory size An interrupt is generated if TCIE and TC are both set and it is cl...

Page 727: ...g access starts the same as indirect read sequence BUSY stays high even between periodic intervals Polling match mode SPMOD controls the comparison match mode if SPMOD 1 the AND mode is selected In this mode status match flag SM is set only when there is a match on all the unmasked bits While if SPMOD 0 the OR mode is selected In this mode SM is set if there is a match on any of the unmasked bit I...

Page 728: ... a transfer BUSY goes high before CSN falls and is cleared when a timeout occurred or abort disable is issued 22 4 4 FMC mode This mode is supported based on memory map mode with a highest priority QSPI read address is wordalign FMCmodewill abort any transfer except status pollingmode But when an indirect write mode is aborted QSPI will not access FMC mode immediately because of the time requireme...

Page 729: ...e shifted half one of SCK cycle using SSAMPLE bit DMAEN bit enables the DMA requests which is generatedaccording to FIFO level and FTL bits 22 6 Security description If there are option bytes the global TrustZone system security is activated by setting the TZEN bit in FMC_OBR register If there are no option bytes the global TrustZone system security is activated by setting the TZEN bit in EFUSE_TZ...

Page 730: ...dsequenceskipinstructionphase until QSPI_TCFG is accessedagain SIOO has no affect when IMOD 00 NOTE Softwareshouldmakesurethat when useSIOOfunction basic modeand FMCmode cannot be overlapped until one transfer is fully completed or the result cannot be predicted 22 8 Busy BUSY bit is set once the QSPI start to operate the external flash memory In indirect mode BUSY is reset once the command phase ...

Page 731: ...staus polling mode don t match until the timeout cnt for staus polling mode is deincresed to zero will generate an AHB error 22 10 QSPI interrupts Table 22 4 QSPI interrupt requests Flag Description Clear method Interrupt enable bit FT FIFO threshold By hardw are FTIE TC Transfer complete Set TCC bit in QSPI_STATC register TCIE TERR Transfer error Set TERRC bit in QSPI_STATC register TERRIE TMOUT ...

Page 732: ... FAHB 1 FCLK FAHB 2 2 FCLK FAHB 3 255 FCLK FAHB 256 For odd clock division factors CLK s duty cycle is not 50 The clock signal remains low one cycle longer than it stays high This field can be modified only w hen BUSY 0 23 SPMOD Status Polling match mode 0 AND match mode SM is set if all the unmasked bits received from the Flash memory match the corresponding bits in the match register 1 OR match ...

Page 733: ... 1 or more free bytes available to be w ritten to in the FIFO 1 FT is set if there are 2 or more free bytes available to be w ritten to in the FIFO 15 FT is set if there are 16 free bytes available to be w ritten to in the FIFO In indirect read mode FMOD 01 0 FT is set if there are 1 or more valid bytes that can be read from the FIFO 1 FT is set if there are 2 or more valid bytes that can be read ...

Page 734: ...served Must be kept at reset value 1 ABORT Abort request This bit stop the current command It is automatically cleared once the abort is complete When FMC mode is used this bit is set by hardw are to stop the normal transfer and cleared w hen it is ready to w orkin FMC mode User should not w rite this bit in this mode In polling mode or memory mapped mode this bit also reset the SPS bit or the DMA...

Page 735: ...N stays high for at least 2 cycles betw een Flash memory commands 7 CSN stays high for at least 8 cycles betw een Flash memory commands This field can be modified only w hen BUSY 0 7 1 Reserved Must be kept at reset value 0 CKMOD This bit indicates the SCK level w hen QSPI is free 0 CLK must stay low w hile CSN is high QSPI is free 1 CLK must stay high w hile CSN is high QSPI is free This field ca...

Page 736: ... 7 TCIE Transfer complete interrupt enable This bit enables the transfer complete interrupt 0 Interrupt disable 1 Interrupt enabled 6 TERRIE Transfer error interrupt enable This bit enables the transfer error interrupt 0 Interrupt disable 1 Interrupt enabled 5 WS Wrong start sequence flag This bit is set w hen a w rong secure start sequence is detected This bit is cleared by w riting 1 to WSC 4 TM...

Page 737: ...C Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WSC TMOUTC SMC Reserved TCC TERRC w w w w w Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 5 WSC Clear w rong start sequence flag Writing 1 clears the WS flag in the QSPI_STAT register 4 TMOUTC Clear timeo...

Page 738: ...01 2 bytes are to be transferred 0x0000_0002 3 bytes are to be transferred 0x0000_0003 4 bytes are to be transferred 0xFFFF_FFFD 4 294 967 294 4G 2 bytes are to be transferred 0xFFFF_FFFE 4 294 967 295 4G 1 bytes are to be transferred 0xFFFF_FFFF undefined length all bytes until the end of Flash memory as defined by FMSZ are to be transferred Continue reading indefinitely if FMSZ 0x1F This field h...

Page 739: ...his field can be w ritten only w hen BUSY 0 25 24 DATAMOD 1 0 Data mode This field defines the data phase s mode of operation 00 No data 01 Data on a single line 10 Data on tw o lines 11 Data on four lines This field also determines the dummy phase mode of operation This field can be w ritten only w hen BUSY 0 23 Reserved must be kept at reset value 22 18 DUMYC 4 0 Number of dummy cycles This fiel...

Page 740: ...n tw o lines 11 Address on four lines This field can be w ritten only w hen BUSY 0 9 8 IMOD 1 0 Instruction mode This field defines the instruction phase mode of operation 00 No instruction 01 Instruction on a single line 10 Instruction on tw o lines 11 Instruction on four lines This field can be w ritten only w hen BUSY 0 7 0 INSTRUCTION 7 0 Instruction Command information to be send to the flash...

Page 741: ...Descriptions 31 0 ALTE 31 0 Alternate Bytes Optional data to be send to the flash memory This field can be w ritten only w hen BUSY 0 22 11 9 Data register QSPI_DATA Address offset 0x20 Reset value 0x0000 0000 This register can be accessed by word half word byte 32 bits 16 bits 8 bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA 15 0 rw B...

Page 742: ...27 26 25 24 23 22 21 20 19 18 17 16 Reserved DMAEN rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WSIE TMOUTIE SMIE FTIE TCIE TERRIE WS TMOUT SM FT TC TERR rw rw rw rw rw rw r r r r r r Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 16 DMAEN DMA enable In indirect mode DMA can be used to transfer data via QSPI_DATA DMA transfers are initiated w hen FT is set 0 DMA disabled ...

Page 743: ...flag This bit is set in status polling mode w hen the unmasked received data matches the expected value It is cleared by w riting 1 to SMC 2 FT FIFO threshold flag In indirect mode this bit is set w hen the FIFO threshold has been reached or if the FIFO is not empty after the last read operation from the Flash memory In automatic polling mode this bit is set every time the status register is read ...

Page 744: ...Must be kept at reset value 1 TCC Clear transfer complete flag Writing 1 clears the TC flag in the QSPI_STAT register 0 TERRC Clear transfer error flag Writing 1 clears the TERR flag in the QSPI_STAT register 22 11 12 Secure Data length register QSPI_DTLEN_SEC Address offset 0x110 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 D...

Page 745: ... 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SIOO FMOD 1 0 DATAMOD 1 0 Reserved DUMYC 4 0 ALTESZ 1 0 rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALTEMOD 1 0 ADDRSZ 1 0 ADDRMOD 1 0 IMOD 1 0 INSTRUCTION 7 0 rw rw rw rw rw Bits Fields Descriptions 31 29 Reserved must be kept at reset value 28 SIOO Send instruction only onc...

Page 746: ...ytes size 00 8 bit alternate byte 01 16 bit alternate bytes 10 24 bit alternate bytes 11 32 bit alternate bytes This field can be w ritten only w hen BUSY 0 15 14 ALTEMOD 1 0 Alternate bytes mode This field defines the alternate bytes phase mode of operation 00 No alternate bytes 01 Alternate bytes on a single line 10 Alternate bytes on tw o lines 11 Alternate bytes on four lines This field can be...

Page 747: ...s register QSPI_ADDR_SEC Address offset 0x118 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR 15 0 rw Bits Fields Descriptions 31 0 ADDR 31 0 Address Address to be send to the external Flash memory This bits can only be w ritten w hen BUSY 0 and memory mapped mode is not co...

Page 748: ...ry In indirect w rite mode data w ritten to this register is stored on the FIFO before sent to the Flash memory If the FIFO is full a w rite operation is stalled until the FIFO has enough space In indirect read mode reading this register gives the data received from the Flash memory If the FIFO does not have as many bytes as requested by the read command and if BUSY 1 the read operation is stalled...

Page 749: ...atch register QSPI_ STATMATCH Address offset 0x28 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MATCH 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MATCH 15 0 rw Bits Fields Descriptions 31 0 MATCH 31 0 Status match Expected value to be compared w ith the masked status register to get a match This field can be w ritten only w ...

Page 750: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMOUT 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 TMOUT 15 0 Timeout cycle When the FIFO is full in memory mapped mode this field indicates how many SCK cycles the QSPI w aits for next access keeping CSN low This field can be w ritten only w hen BUSY 0 22 11 21 FIFO flush register QSPI_FLUSH Address offset 0x34 Reset value 0x...

Page 751: ...rted until this w ait cnt is deincreased to zero 22 11 23 Timeout for staus polling mode register QSPI_SPTMOUT Address offset 0x3C Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SPTMOUT 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPTMOUT 15 0 rw Bits Fields Descriptions 31 0 SPTMOUT 31 0 Timeout cnt w hen a FMC transfer trys ...

Page 752: ...ds Descriptions 31 1 Reserved Must be kept at reset value 0 FMCSEC FMC mode security When set the registers of FMC mode QSPI_CTLF QSPI_TCFGF QSPI_ALTEF QSPI_BYTE_CNT are secure 22 11 25 Control register in FMC mode QSPI_CTLF Address offset 0x80 Reset value 0x8000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PSCF 7 0 CKMODF Reserved CSHCF 2 0 rw ...

Page 753: ...ast 8 cycles betw een Flash memory commands This field can be modified only w hen BUSY 0 15 12 SCKDVALUEF 3 0 sck delay value in FMC mode this only useful w hen SCK_DENF is enable and SSAMPLEF is set 11 7 Reserved Must be kept at reset value 6 SCKDENF SCK delay enable w hen read data from flash in FMC mode it is only useful w hen SSAMPLEF is 1 0 SCK delay disabled 1 SCK delay enabled 5 4 SSAMPLEF ...

Page 754: ...he data phase s mode of operation 00 No data 01 Data on a single line 10 Data on tw o lines 11 Data on four lines This field also determines the dummy phase mode of operation This field can be w ritten only w hen BUSY 0 23 Reserved Must be kept at reset value 22 18 DUMYCF 4 0 Number of dummy cycles in FMC mode This field defines the duration of the dummy phase This field can be w ritten only w hen...

Page 755: ...Instruction mode in FMC mode This field defines the instruction phase mode of operation 00 No instruction 01 Instruction on a single line 10 Instruction on tw o lines 11 Instruction on four lines This field can be w ritten only w hen BUSY 0 7 0 INSTRUCTIONF 7 0 Instruction in FMC mode Command information to be send to the flash memory This field can be w ritten only w hen BUSY 0 22 11 27 Alternate...

Page 756: ...ter can be read by both privileged and unprivileged access When the system is secure TZEN 1 this register can be read by secure and non secure access It is write protected against non secure write access when the bit FMCSEC is set in the QSPI_FMC_SECCFGregister A non secure write access is ignored and generates an illegal access event This register can be accessed by word 32 bit 31 30 29 28 27 26 ...

Page 757: ...tten by privileged access only If the QSPI FMC mode is not secure the PRIV bit can be w ritten by a secure or non secure privileged access If the QSPI FMC mode is secure the PRIV bit can be w ritten only by a secure privileged access A non secure w rite access is ignored and generates an illegal access event A secure unprivileged w rite access on PRIV bit is ignored ...

Page 758: ...owing MMC Full support for Multimedia Card System Specification Version 4 2 and previous versions Card and three different data bus modes 1 bit default 4 bit and 8 bit SD Card Full support for SD Memory Card Specifications Version 2 0 SDI O Full support for SD I OCardSpecificationVersion2 0 cardandtwodifferent data bus modes 1 bit default and 4 bit CE ATA Full compliance with CE ATA digital protoc...

Page 759: ...commands These commands send a data block successfully by CRC bits Both read and write operations allow either single or multiple block transmission A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read The basic transaction on the bus is the command response transaction refer to Figure 23 1 SDIO no response and no data operations ...

Page 760: ...eration Host to Device Host to Device Data transfers to from SD memory cards SD I O cards both IO only card and combo card and CE ATA device are done in data blocks Data transfers to from MMC are done in data blocks or streams Figure23 4 SDIO sequential read operation and Figure 23 5 SDIO sequential write operation are the stream read and write operation Figure 23 4 SDIO sequential read operation ...

Page 761: ...apter contains control unit command unit and data unit and generates signals to cards The signals is descript bellow SDIO_CK The SDIO_CK is the clock provided to the card Each cycle of this signal directs a one bit transfer on the command line SDIO_CMD and on all the data lines SDIO_D The SDIO_CK frequency can vary between 0 MHz and 20 MHz for a Multimedia Card V3 31 between 0 and 48 MHz for a Mul...

Page 762: ...t iscontrolledby SDIO_PWRCTL register which implements power off or power on The power saving mode configured by setting CLKPWRSAV bit in SDIO_CLKCTL register which implements close the SDIO_CK when the bus is idle The clock management generates SDIO_CK to card The SDIO_CK is generated by a divider of SDIOCLK when CLKBYP bit in SDIO_CLKCTL register is 0 or directly SDIOCLK when CLKBYP bit in SDIO_...

Page 763: ... the host command and the response CS_Pend Waits for the end of data transfer 1 The data transfer complete CS_Send 2 CSM disabled CS_Idle CS_Send Sending the command 1 The command transmitted has response CS_Wait 2 The command transmitted doesn t have response CS_Idle 3 CSM disabled CS_Idle CS_Wait Wait for the start bit of the response 1 Receive the response detected the start bit CS_Receive 2 Ti...

Page 764: ...ADIR in SDIO_DATACTL register is 0 or receive data from card when DATADIR in SDIO_DATACTL register is 1 The data unit also generates the data status flags defined in SDIO_STAT register Data state machine DS_Idle The data unit is inactive w aiting for send and receive 1 DSM enabled and data transfer direction is from host to card DS_WaitS 2 DSM enabled and data transfer direction is from card to ho...

Page 765: ... disabled DS_Idle 23 4 2 APB2 interface The APB2 interface implements access to SDIO registers data FIFO and generates interrupt and DMA request It includes a data FIFO unit registers unit and the interrupt DMA logic The interrupt logic generates interrupt when at least one of the selected status flags is high Aninterrupt enableregisteris provided toallowthelogic togeneratea correspondinginterrupt...

Page 766: ...DMA enabled BLKSZ with 0x9 512 bytes Other bits don t care Wait for DTBLKEND flag is set Check that no channels are still enabled by polling the DMA Interrupt Flag register It consists the following subunits Register unit The register unit which contains all system registers generates the signals to control the communication between the controller and card Data FIFO The data FIFO unit has a data b...

Page 767: ...egister defines the card properties and selected modes It is 512 bytes long The most significant 320 bytes are the Properties segment which defines the card capabilities and cannot be modified by the host The lower 192 bytes are the Modes segment which defines the configuration the card is working in These modes can be changed by the host by means of the SWITCH command The host can use CMD8 just M...

Page 768: ...47 46 45 40 39 8 7 1 0 Width 1 1 6 32 7 1 Value 0 1 x x x 1 Description start bit transmission bit command index argument CRC7 end bit A commandalways startswithastart bit always 0 followedby thebit indicatingthedirection of transmission host 1 The next 6 bits indicate the index of the command this value being interpreted as a binary coded number between 0 and 63 Some commands need an argument e g...

Page 769: ...ll support the MMC commands required to achieve the transfer state during device initialization Other interface configuration settings such as bus width may require additional MMC commands also be supported See the MMC reference CE ATA makes use of the following MMC commands CMD0 GO_IDLE_STATE CMD12 STOP_TRANSMISSION CMD39 FAST_IO CMD60 RW_MULTIPLE_REGISTER CMD61 RW_MULTIPLE_BLOCK GO_IDLE_STATE CM...

Page 770: ...CMD53 CMD57 and ACMDx CMD14 M CMD15 M CMD16 M CMD17 M CMD18 M CMD19 M CMD20 M CMD23 M CMD24 M CMD25 M CMD26 M CMD27 M CMD28 M CMD29 M CMD30 M CMD32 M CMD33 M CMD34 O CMD35 O CMD36 O CMD37 O CMD38 M CMD39 CMD40 CMD42 CMD50 O CMD52 O CMD53 O CMD55 M CMD56 M CMD57 O CMD60 M CMD61 M ACMD6 M ACMD13 M ACMD22 M ACMD23 M ACMD41 M ACMD42 M ACMD51 M ...

Page 771: ...hout busy R3 SEND_OP_COND Asks the card in idle state to send its Operating Conditions Register contents in the response on the CMD line CMD2 bcr 31 0 stuff bits R2 ALL_SEND_CID Asks any card to send the CID numbers on the CMD line any card that is connected to the host w ill respond CMD3 bcr 31 0 stuff bits R6 SEND_RELATIVE _ADDR Ask the card to publish a new relative address RCA CMD4 bc 31 16 DS...

Page 772: ...31 0 stuff bits R1 SEND_EXT_CSD For MMC only The card sends its EXT_CSD register as a block of data CMD9 ac 31 16 RCA 15 0 stuff bits R2 SEND_CSD Addressed card sends its card specific data CSD on the CMD line CMD10 ac 31 16 RCA 15 0 stuff bits R2 SEND_CID Addressed card sends its card identification CID on CMD the line CMD12 ac 31 0 stuff bits R1b STOP TRANSMISSION Forces the card to stop transmi...

Page 773: ...e commands Alw ays 512 Bytes fixed block length is used In both cases if block length is set larger than 512Bytes the card sets the BLOCK_LEN_ERROR bit CMD17 adtc 31 0 data address R1 READ_SINGLE_B LOCK In the case of a Standard Capacity SD and MMC this command reads a block of the size selected by the SET_BLOCKLEN command In the case of a High Capacity Card block length is fixed 512 Bytes regardl...

Page 774: ... CSD register Table 23 7 Block Oriented write commands class4 Cmd index type argument Response format Abbreviation Description CMD16 ac 31 0 block length R1 SET_BLOCKLEN See description in Table 23 5 Block Oriented read commands class 2 CMD23 ac 31 16 set to 0 15 0 number of blocks R1 SET_BLOCK_ COUNT Defines the number of blocks w hich are going to be transferred in the immediately succeeding mul...

Page 775: ...t supported then the block length default block length given in CSD 2 Data address is in byte units in a Standard Capacity SD Memory Card and in block 512 Byte units in a High Capacity SD Memory Card Table 23 8 Erase commands class5 Cmd index type argument Response format Abbreviation Description CMD32 ac 31 0 data address R1 ERASE_WR_BLK _START Sets the address of the first w rite block to be era...

Page 776: ...rd does not support this command CMD29 ac 31 0 data address R1b CLR_WRITE_PROT If the card provides w rite protection features this command clears the w rite protection bit of the addressed group CMD30 adtc 31 0 w rite protect data address R1 SEND_WRITE_PRO T If the card provides w rite protection features this command asks the card to send the status of the w rite protection bits Note 1 High Capa...

Page 777: ...gned to OCR 30 ACMD42 ac 31 1 stuff bits 0 set_cd R1 SET_CLR_CAR D_DETECT Connect 1 Disconnect 0 the 50K pull up resistor on CD D3 pin 1 of the card ACMD51 adtc 31 0 stuff bits R1 SEND_SCR Reads the SD Configuration Register SCR CMD55 ac 31 16 RCA 15 0 stuff bits R1 APP_CMD Indicates to the card that the next command is an application specific command rather than a standard command CMD56 adtc 31 1...

Page 778: ...ard and a register and provides the data for w riting if the w rite flag is set The R4 response contains data read from the addressed register if the w rite flag is cleared to 0 This command accesses application dependent registers w hich are not defined in the MMC standard CMD40 bcr 31 0 stuff bits R5 GO_IRQ_STATE Sets the system into interrupt mode CMD52 adtc 31 R W Flag 30 28 Function Number 27...

Page 779: ...for SD I O card Table 23 13 Switch function commands class10 Cmd index type argument Response format Abbreviation Description CMD6 adtc 31 Mode 0 Check function 1 Sw itch function 30 24 reserved 23 20 reserved for function group 6 0h or Fh 19 16 reserved for function group 5 0h or Fh 15 12 reserved for function group 4 0h or Fh 11 8 reserved for function group 3 0h or Fh 7 4 function group 2 for c...

Page 780: ...gth others are all 48 bits length Figure 23 8 Response Token Format 0 1 Content CRC 1 Total length 48 bits 0 1 Content CID or CSD CRC 1 Total length 136 bits A response always starts with a start bit always 0 followed by the bit indicating the direction of transmission card 0 A value x in the tables below indicates a variable entry All responses except for the type R3 are protected by a CRC Every ...

Page 781: ...ed the reserved bit 0 of these registers is replaced by the end bit of the response Table 23 15 Response R2 Bit position 135 134 133 128 127 1 0 Width 1 1 6 127 1 Value 0 0 111111 x 1 description start bit transmission bit reserved CID or CSD register and internal CRC7 end bit R3 OCR register Code length is 48 bits The contents of the OCR register are sent as a response toACMD41 SD memory CMD1 MMC...

Page 782: ...si on bit Reserv ed C Number of I O functions Memory Present Stuff Bits S18A I O OCR Reserv ed end bit R5 Interrupt request For MMC only Code length is 48 bits If the response is generated by the host the RCA field in the argument will be 0x0 Table 23 19 Response R5 for MMC Bit position 47 46 45 40 39 8 Argument field 7 1 0 Width 1 1 6 16 16 7 1 Value 0 0 101000 x x x 1 description start bit trans...

Page 783: ...card supports The card that accepted the supplied voltage returns R7 response In the response the card echoes back both the voltage range and check pattern set in the argument Table 23 22 Response R7 Bit position 47 46 45 40 39 20 19 16 15 8 7 1 0 Width 1 1 6 20 4 8 7 1 Value 0 0 001000 00000h x x x 1 description start bit transmission bit CMD8 Reserved bits Voltage accepted echo back of check pat...

Page 784: ...data packet format Figure 23 11 8 bit data buswidth Start bit End bit 1st Byte 2nd Byte 3rd Byte nth Byte 0 CRC 1 D7 0 CRC 1 D6 0 CRC 1 D5 0 CRC 1 D4 0 CRC 1 D3 0 CRC 1 D2 0 CRC 1 D1 0 CRC 1 D0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b7 b6 b5 b4 b7 b6 b5 b4 b7 b6 b5 b4 b7 b6 b5 b4 b3 b2 b1 b0 23 5 5 Two status fields of the card The SD Memory supports two status fields and others just support the firs...

Page 785: ...tions are detected by the card during the command interpretation and validation phase Response Mode X Exceptions are detected by the card during command executionphase Execution Mode Clear condition A According tocurrent state of the card B Always related to the previous command Reception of a valid command will clear it with a delay of one command C Cleared by read Table 23 23 Card status Bits Id...

Page 786: ...f the previous command failed B 22 ILLEGAL_COMMAND ER 0 no error 1 error Command not legal for the card state B 21 CARD_ECC_FAILED ERX 0 success 1 failure Card internal ECC w as applied but failed to correct the data C 20 CC_ERROR ERX 0 no error 1 error Internal card controller error C 19 ERROR ERX 0 no error 1 error A general or an unknow n error occurred during the operation C 18 UNDERRUN ERX 0 ...

Page 787: ...nd by 4 transfer 5 send data 6 receive data 7 programming 8 disconnect 9 14 reserved 15 reserved for I O mode The state of the card w hen receiving the command If the command execution causes a state change it w ill be visible to the host in the response to the next command The four bits are interpreted as a binary coded number betw een 0 and 15 B 8 READY_FOR_DATA SX 0 not ready 1 ready Correspond...

Page 788: ...ibed below The sameabbreviationfor type and clearcondition wereusedas for theCard Status above Table 23 24 SD status Bits Identifier Type Value Description Clear Condition 511 5 10 D_BUS_WIDTH SR 00 1 default 01 reserved 10 4 bit w idth 11 reserved Show s the currently defined data bus w idth that w as defined by SET_BUS_WIDTH command A 509 SECURED_MODE SR 0 Not in the mode 1 In Secured Mode Card ...

Page 789: ...ed offset value added to erase time See below A 399 3 12 reserved 311 0 reserved for manufacturer SIZE_OF_PROTECTED_AREA Setting this field differs between SDSC and SDHC SDXC In case of SDSC Card the capacity of protected area is calculated as follows ProtectedArea SIZE_OF_PROTECTED_AREA_ MULT BLOCK_LEN SIZE_OF_PROTECTED_AREAis specified by the unit in MULT BLOCK_LEN In case of SDHC and SDXC Cards...

Page 790: ... PERFORMANCE_M OVE Value Definition 00h Sequential Write 01h 1 MB sec 02h 2 MB sec FEh 254 MB sec FFh Infinity AU_SIZE This 4 bit field indicates AU Size and the value can be selected from 16 KB Table 23 26 AU_SIZE field AU_SIZE Value Definition 0h Not Defined 1h 16 KB 2h 32 KB 3h 64 KB 4h 128 KB 5h 256 KB 6h 512 KB 7h 1 MB 8h 2 MB 9h 4 MB Ah 8 MB Bh 12 MB Ch 16 MB Dh 24 MB Eh 32 MB Fh 64 MB The m...

Page 791: ...ot supported 0001h 1 AU 0002h 2 AU 0003h 3 AU FFFFh 65535 AU ERASE_TIMEOUT This 6 bit field indicates the TERASE and the value indicates erase timeout from offset when multipleAUs are erased as specified by ERASE_SIZE The range of ERASE_TIMEOUT can be defined as up to 63 seconds and the card manufacturer can choose any combination of ERASE_SIZE and ERASE_TIMEOUT depending on the implementation Onc...

Page 792: ...d for memory or the memory portion of Combo cards In order to reset an I O only card or the I O portion of a combo card use CMD52 to write 1 to the RES bit in the CCCR Cards in Inactive State are not affected by this command After power on by the host all cards are in Idle State includingthe cards that have been in Inactive Statebefore Afterpower onor CMD0 all cards CMDlines are ininput mode waiti...

Page 793: ... 1 Check if the card is connected 2 Identify the card type SD MMC CE ATA or SD I O Send CMD5 first If a response is received then the card is SD I O If not sendACMD41 if a response is received then the card is SD Otherwise the card is an MMC or CE ATA 3 Initialization the card according to the card type Use a clock source with a frequency FOD that is 400 KHz and use thefollowing command sequence S...

Page 794: ...gister and while ignoring all further data transfer The write operation will also be aborted if the host tries to write data on a write protected area In this case however the card will set the WP_VIOLATION bit in the status register Programming of the CID and CSD registers does not require a previous block length setting The transferred data is also CRC protected If a part of the CSD or CID regis...

Page 795: ...block transfer if the byte count is 0 the software must send the STOP command If the byte count is not 0 then upon completion of a transfer of a given number of bytes the host should send the STOP command 23 6 4 Single block or multiple block read Block read is block oriented data transfer The basic unit of data transfer is a block whose maximum size is defined in the CSD READ_BL_LEN it is always ...

Page 796: ... by sending a STOP command 6 The software should read data from the FIFO and make space in the FIFO for receiving more data 7 When a DTEND interrupt is received the software should read the remaining data in the FIFO 23 6 5 Stream write and stream read MMC only Stream write Stream write CMD20 starts the data transfer from the host to the card beginning from the starting address until the host issu...

Page 797: ... has an execution delay due to the serial command transmission The data transfer stops after the end bit of the stop command If the host provides an out of range address as an argument to CMD11 the card will reject the command remain in Transfer state and respond with theADDRESS_OUT_OF_RANGE bit set Notethat thestream readcommandworks only ona 1bit bus configuration on D0 If CMD11 is issued in oth...

Page 798: ... ERASE_GROUP_END CMD36 ERASE_WR_BLK_END CMD33 command and finally it starts the erase process by issuing the ERASE CMD38 command The address field in the erase commands is an Erase Group address in byte units The card will ignore all LSB s below the Erase Group size effectively rounding the address down to the Erase Group boundary If an erase command CMD35 CMD36 and CMD38 is received out of the de...

Page 799: ...e protected by setting the permanent or temporary write protect bits in the CSD Some cards support write protection of groups of sectors by setting the WP_GRP_ENABLE bit in the CSD It is defined in units of WP_GRP_SIZE erase groups as specified in the CSD The SET_WRITE_PROT command sets the write protection of the addressed write protected group and the CLR_WRITE_PROT command clears the write prot...

Page 800: ... 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Reserved all set to 0 ERASE LOCK_UNLOCK CLR_PWD SET_PWD 1 PWDS_LEN 2 Passw ord data PWD PWDS_LEN 1 ERASE 1 Defines Forced Erase Operation In byte 0 bit 3 will be set to 1 all other bits shall be 0 All other bytes of this command will be ignored by the card LOCK UNLOCK 1 Locks the card 0 Unlock the card note that it is valid to set this bit together wi...

Page 801: ...opriate data block size on thedata line including the 16 bit CRC The data block shall indicate the mode CLR_PWD the length PWDS_LEN and the password itself If the PWD and PWD_LEN content match the sent password and its size then the content of the PWD register is cleared and PWD_LEN is set to 0 If the password is not correct then the LOCK_UNLOCK_FAILED error bit will be set in the status register ...

Page 802: ...ple CMD53 operation to temporarily stall the data transfer while allowing the host to send commands to any function within the SD I O card To determine if a card supports the Read Wait protocol the host shall test SRW capability bit in the Card Capability byte of the CCCR The timing for Read Wait is basedontheInterrupt Period If a carddoes not support theRead Wait protocol the only means a host ha...

Page 803: ...Combo card there are multiple devices I O and memory that share access to the SD bus In order to allow the sharing of access to the host among multiple devices SD I O and combo cards can implement the optional concept of suspend resume If a card supports suspend resume the host may temporarily halt a data transfer operation to one function or memory suspend in order to free the bus for a higher pr...

Page 804: ... either recognized and acted upon by the host or de assertedduetotheendof theInterrupt Period Oncethehost has servicedtheinterrupt it is cleared via function unique I O operation When setting the SDIO_DATACTL 11 bit SD I O interrupts can detect on the SDIO_D 1 line Figure 23 15 Read Interrupt cycle timing shows the timing of the interrupt period for single data transaction read cycles Figure 23 15...

Page 805: ...eceive command completion signal Send command completion disable signal The SDIO supports these operations only when SDIO_CMDCTL 14 is set Command completion signal CE ATA defines a command completion signal that the device uses to notify the host upon normal ATA command completion or when ATA command termination has occurred due to an error condition the device has encountered If the enable CMD c...

Page 806: ...etion signal disable when it has received an R1b response for an outstanding RW_MULTIPLE_BLOCK CMD61 command Commandcompletionsignal disableissent 8bit cyclesafterthereceptionofashort response if the enable CMDcompletion bit SDIO_CMDCTL 12 is not set andthe not interrupt Enable bit SDIO_CMDCTL 13 is reset Figure 23 19 The operation for command completion disable signal CMD Nrc Ncr CMD S E Response...

Page 807: ...bits control the SDIO state card input or output 00 SDIO pow er off SDIO cmd data state machine reset to IDLE clock to card stopped no cmd data output to card 01 Reserved 10 Reserved 11 SDIO Pow er on Note Betw een Tw o w rite accesses to this register it needs at least 3 SDIOCLK 2 pclk2 w hich used to sync the registers to SDIOCLK clock domain 23 8 2 Clock control register SDIO_CLKCTL Address off...

Page 808: ... control bit 00 1 bit SDIO card bus mode selected 01 4 bit SDIO card bus mode selected 10 8 bit SDIO card bus mode selected 10 CLKBYP Clock bypass enable bit This bit defines the SDIO_CK is directly SDIOCLK or not 0 NO bypass the SDIO_CK refers to DIV bits in SDIO_CLKCTL register 1 Clock bypass the SDIO_CK is directly from SDIOCLK SDIOCLK 1 9 CLKPWRSAV SDIO_CK clock dynamic sw itch on off for pow ...

Page 809: ...mand message contains an argument this field must update before w ritting SDIO_CMDCTL register w hen sending a command 23 8 4 Command control register SDIO_CMDCTL Address offset 0x0C Reset value 0x0000 0000 The SDIO_CMDCTL register contains the command index and other command control bits to control command state machine This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22...

Page 810: ... Command state machine enable 9 WAITDEND Waits for ends of data transfer If this bit is set the command state machine starts to send a command must w ait the end of data transfer 0 no effect 1 Wait the end of data transfer 8 INTWAIT Interrupt w ait instead of timeout This bit defines the command state machine to w ait card interrupt at CS_Wait state in command state machine If this bit is set no c...

Page 811: ... short response of R3 the content of this register is undefined 23 8 6 Response register SDIO_RESPx x 0 3 Address offset 0x14 4 x x 0 3 Reset value 0x0000 0000 These register contains the content of the last card response received This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESPx 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESPx 15 0 r Bits Fie...

Page 812: ...data timeout period count by SDIO_CK When the DSM enter the state WaitR or BUSY the internal counter w hich loads from this register starts decrement The DSM timeout and enter the state Idle and set the DTTMOUT flag w hen the counter decreases to 0 Note The data timer register and the data length register must be updated before being w ritten to the data control register w hen need a data transfer...

Page 813: ...28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IOEN RWTYPE RWSTOP RWEN BLKSZ 3 0 DMAEN TRANSM OD DATADIR DATAEN rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 IOEN SD I O specific function enable SD I O only 0 Not SD I O specific function 1 SD I O specific function 10 RWTYPE Read w ait type SD I O on...

Page 814: ... 0 DATAEN Data transfer enable bit Write 1 to this bit to start data transfer regardless this bit is 0 or 1 The DSM moves to Readw ait state if RWEN is set or to the WaitS WaitR state depend on DATADIR bit Start a new data transfer it not need to clear this bit to 0 Note Betw een Tw o w rite accesses to this register it needs at least 3 SDIOCLK 2 pclk2 w hich used to sync the registers to SDIOCLK ...

Page 815: ...he hardware logic This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved ATAEND SDIOINT RXDTVA L TXDTVAL RFE TFE RFF TFF r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFH TFH RXRUN TXRUN CMDRUN DTBLKE ND STBITE DTEND CMDSEN D CMDREC V RXORE TXURE DTTMOU T CMDTMO UT DTCRCE RR CCRCER R r r r r r r r r r r r r r r r r Bits Fields Descriptions ...

Page 816: ...equired 6 CMDRECV Command response received CRC check passed 5 RXORE Received FIFO overrun error occurs 4 TXURE Transmit FIFO underrun error occurs 3 DTTMOUT Data timeout The data timeout period depends on the SDIO_DATATO register 2 CMDTMOUT Command response timeout The command timeout period has a fixed value of 64 SDIO_CK clock periods 1 DTCRCERR Data block sent received CRC check failed 0 CCRCE...

Page 817: ...STBITE flag clear bit Write 1 to this bit to clear the flag 8 DTENDC DTEND flag clear bit Write 1 to this bit to clear the flag 7 CMDSENDC CMDSEND flag clear bit Write 1 to this bit to clear the flag 6 CMDRECVC CMDRECV flag clear bit Write 1 to this bit to clear the flag 5 RXOREC RXORE flag clear bit Write 1 to this bit to clear the flag 4 TXUREC TXURE flag clear bit Write 1 to this bit to clear t...

Page 818: ...terrupt enable Write 1 to this bit to enable the interrupt 22 SDIOINTIE SD I O interrupt received interrupt enable Write 1 to this bit to enable the interrupt 21 RXDTVALIE Data valid in receive FIFO interrupt enable Write 1 to this bit to enable the interrupt 20 TXDTVALIE Data valid in transmit FIFO interrupt enable Write 1 to this bit to enable the interrupt 19 RFEIE Receive FIFO empty interrupt ...

Page 819: ...nterrupt enable Write 1 to this bit to enable the interrupt 5 RXOREIE Received FIFO overrun error interrupt enable Write 1 to this bit to enable the interrupt 4 TXUREIE Transmit FIFO underrun error interrupt enable Write 1 to this bit to enable the interrupt 3 DTTMOUTIE Data timeout interrupt enable Write 1 to this bit to enable the interrupt 2 CMDTMOUTIE Command response timeout interrupt enable ...

Page 820: ...nd start count decrement w hen a w ord w rite to or read from the FIFO 23 8 15 FIFO data register SDIO_FIFO Address offset 0x80 Reset value 0x0000 0000 This register occupies 32 entries of 32 bit words the address offset is from 0x80 to 0xFC This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIFODT 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFODT 1...

Page 821: ...ation Protocol and SRP Session Request Protocol Supports all the 4 types of transfer control bulk interrupt and isochronous Includes a USB transaction scheduler in host mode to handle USB transaction request efficiently Includes a 1 25KB FIFO RAM Supports 8 channels in host mode Includes 2 transmit FIFOs periodic and non periodic and a receive FIFO shared by all channels in host mode Includes 4 tr...

Page 822: ...king modes USBFS can operate as a host a device or a DRD Dual role Device it contains an internal full speed PHY The maximum speed supported by USBFS is full speed The internal PHY supports Full Speed and Low Speed in host mode supports Full speed in device mode and supports OTG mode with HNP and SRP The USB clock used by the USBFS shouldbe48MHz The48MHz USB clock is generatedfrom internal clocksi...

Page 823: ...detection circuit is connected to a GPIO pin USBFS continuously monitor the VBUS voltage by the GPIO pin and will immediately switch on the pull up resistor on DP line once that the VBUS voltage rise above the needed valid value This will cause a connection If the VBUS voltage falls below the needed valid value the pull up resistor on DP line will be switched off and a disconnection will happen Th...

Page 824: ...ate After PP bit is set by software the internal USB PHY is powered on and the USB port changes into disconnected state After a connection is detected USB port changes into connected state The USB port changes into enabled state after a port reset is performed on USB bus Figure 24 4 State transition diagram of host port Power off Dis connected Connected Enabled set PP bit clear PP bit or VBUS is n...

Page 825: ... set and the USBFS wake up interrupt will be triggered if a host in suspend state detects a remote wakeup signal SOF generate USBFS sends SOF tokens on USB bus in host mode As described in USB 2 0 protocol SOF packets are generated by the host controller or hub transaction translator every 1ms in full speed links Each time after USBFS enters into enabled state it will send the SOF packet periodica...

Page 826: ... queue If this is a channel disable request it immediately disables the channel and prepares to process the next entry If the current request is a transaction request and the USB bus time is enough for this transaction USBFS will employ SIE to generate this transaction on USB bus When the required bus time for the current request is not enough in the current frame and if this is a periodic request...

Page 827: ...y switchoffthepull upresistor sothat USB host will detect adisconnectiononUSB bus SOF tracking When USBFS receives a SOF packet on USB bus it will trigger a SOF interrupt and begin to count the bus time using local USB clock The frame number of the current frame is reported in FNRSOF filedinUSBFS_DSTATregister WhentheUSBbus timereachesEOF1orEOF2 point End of Frame described in USB 2 0 protocol USB...

Page 828: ... set and the USBFS will begin to perform HNP protocol on bus and at last the result of HNP is reported in HNPS bit in USBFS_GOTGCS register Besides it is always available to get the current role host or device from COPM bit in USBFS_GINTF register SRP The Session Request Protocol SRP allows a B Device to request the A Device to turn on VBUS and start a session This protocol allows the A Device whi...

Page 829: ... RXFD Start 0x00 End 0x13F USBFS provides a special register area for the internal data FIFO reading and writing Figure 24 6 Host mode FIFO access register map describes the register memory area that the data FIFO can write This area can be read by any channel data FIFO The addresses in the figure are addressedinbytes Eachchannel has itsownFIFOaccessregisterspace although all Non periodic channels...

Page 830: ...Device mode FIFO space in SRAM Rx FIFO Tx FIFO0 Tx FIFO1 IEPTX0RSAR 15 0 IEPTX0FD IEPTX1FD IEPTX1RSAR 15 0 RXFD Start 0x00 End 0x13F Tx FIFO3 IEPTX3FD IEPTX3RSAR 15 0 USBFS provides a special register area for the internal data FIFO reading and writing Figure 24 8 Device mode FIFO access register map describes the register memory area where the data FIFO can write This area can be read by any endp...

Page 831: ... USBFS_GCCFG register according to application s demand 4 Program USBFS_GRFLEN USBFS_HNPTFLEN_DIEP0TFLEN and USBFS_HPTFLEN register to configure the data FIFOs according to application s demand 5 Program USBFS_GINTEN register to enable Mode Fault and Host Port interrupt and set GINTEN bit in USBFS_GAHBCS register to enable global interrupt 6 Program USBFS_HPCS register and set PP bit 7 Wait for a ...

Page 832: ... to enable thechannel Channel disable sequence Software can disable the channel by setting both CEN and CDIS bits at the same time USBFS will generate a channel disable request entry in request queue after the register setting operation When the request entry reaches the top of request queue it is processed by USBFS immediately For OUT channels the specified channel will be disabled immediately Th...

Page 833: ...sponding request queue and decreases the TLEN field in USBFS_HCHxLEN register by the written packet s size 4 When the request entry reaches the top of the request queue USBFS begins to process this request entry If bus time for the transaction indicated by the request entry is enough USBFS starts the OUT transaction on USB bus 5 When the OUT transaction indicated by the request entry finishes on U...

Page 834: ... or USBFS_DOEPxCTL register with desired transfer type packet size etc 2 Program USBFS_DIEPINTENorUSBFS_DOEPINTENregister Setthe desiredinterrupt enable bits 3 Program USBFS_DIEPxLEN or USBFS_DOEPxLEN register PCNT is the number of packets in a transfer and TLEN is the total bytes number of all the transmittedor received packets in a transfer For IN endpoint If PCNT 1 the single packet s size is e...

Page 835: ...et or response with an NAK handshake based on the status of Rx FIFO and register configuration If the transaction finishes successfully USBFS receives and saves the data packet into Rx FIFO successfully and sends ACK handshake on USB bus PCNT in USBFS_DOEPxLEN register is decreased by 1 and theACK flag is triggered otherwise thestatus flags report the transaction result 4 After all the data packet...

Page 836: ...errupt flag Device mode ISOOPDIF Isochronous OUT packet dropped interrupt flag Device mode ENUMF Enumeration finished Device mode RST USB reset Device mode SP USB suspend Device mode ESP Early suspend Device mode GONAK Global OUT NAK effective Device mode GNPINAK Global IN Non Periodic NAK effective Device mode NPTXFEIF Non Periodic Tx FIFO empty interrupt flag Host Mode RXFNEIF Rx FIFO non empty ...

Page 837: ... rw r Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 BSV B Session Valid described in OTG protocol 0 Vbus voltage level of a OTG B Device is below VBSESSVLD 1 Vbus voltage level of a OTG B Device is above VBSESSVLD Note Only accessible in OTG B Device mode 18 ASV A Session valid A host mode transceiver status 0 Vbus voltage level of a OTG A Device is below VASESSVLD 1 Vbus ...

Page 838: ...doesn t response to the HNP request from B Device 0 HNP function is not enabled 1 HNP function is enabled Note Only accessible in host mode 9 HNPREQ HNP request This bit is set by softw are to start a HNP on the USB This bit can be cleared w hen HNPEND bit in USBFS_GOTGINTF register is set by w riting zero to it or clearing the HNPEND bit in USBFS_GOTGINTF register 0 Don t send HNP request 1 Send ...

Page 839: ...O HNPDET Reserved rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved HNPEND SRPEND Reserved SESEND Reserved rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 DF Debounce finish Set by USBFS w hen the debounce during device connection is done Note Only accessible in host mode 18 ADTO A Device timeout Set by USBFS w hen the A Device s w aiting for...

Page 840: ...ue GlobalAHB control and status register USBFS_GAHBCS Address offset 0x0008 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PTXFTH TXFTH Reserved GINTEN rw rw rw Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 PTXFTH Periodic Tx FIFO threshold 0 PTXFE...

Page 841: ... offset 0x000C Reset value 0x0000 0A80 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FDM FHM Reserved rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UTT 3 0 HNPCEN SRPCEN Reserved TOC 2 0 rw r rw r rw rw Bits Fields Descriptions 31 Reserved Must be kept at reset value 30 FDM Force device mode Setting this bit w illforce the core to d...

Page 842: ...bility enable Controls w hether the SRP capability is enabled 0 SRP capability is disabled 1 SRP capability is enabled Note Accessible in both device and host modes 7 3 Reserved Must be kept at reset value 2 0 TOC 2 0 Timeout calibration USBFS alw ays uses time out value required in USB 2 0 w hen w aiting for a packet Application may use TOC 2 0 to add the value is in terms of PHY clock The freque...

Page 843: ...utomatically clears this bit after the flush process completes After setting this bit application should w ait until this bit is cleared before any other operation on USBFS Note Accessible in both device and host modes 4 RXFF Rx FIFO flush Application set this bit to flush data Rx FIFO Hardw are automatically clears this bit after the flush process completes After setting this bit application shou...

Page 844: ... OEPIF IEPIF Reserved rc_w1 rc_w1 rc_w1 rc_w1 r r r rc_w1 rc_w1 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EOPFIF ISOOPDIF ENUMF RST SP ESP Reserved GONAK GNPINAK NPTXFEIF RXFNEIF SOF OTGIF MFIF COPM rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 r r r r rc_w1 r rc_w1 r Bits Fields Descriptions 31 WKUPIF Wakeup interrupt flag This interrupt is triggered w hen a resume signal in device mode or a remote w akeup...

Page 845: ...the flags that causing a port interrupt are cleared Note Only accessible in host mode 23 22 Reserved Must be kept at reset value 21 PXNCIF ISOONCIF Periodic transfer Not Complete Interrupt flag USBFS sets this bit w hen there are periodic transactions for current frame not completed at the end of frame Host mode Isochronous OUT transfer Not Complete Interrupt Flag At the end of a periodic frame de...

Page 846: ...isochronous OUT packet but cannot save it into Rx FIFO because the FIFO doesn t have enough space Note Only accessible in device mode 13 ENUMF Enumeration finished USBFS sets this bit after the speed enumeration finishes Read USBFS_DSTAT register to get the current device speed Note Only accessible in device mode 12 RST USB reset USBFS sets this bit w hen it detects a USB reset signal on bus Note ...

Page 847: ...by w riting 1 Note Accessible in both host and device modes 2 OTGIF OTG interrupt flag USBFS sets this bit w hen the flags in USBFS_GOTGINTF register generate an interrupt Softw are should read USBFS_GOTGINTF register to get the source of this interrupt This bit is cleared after the flags in USBFS_GOTGINTF causing this interrupt are cleared Note Accessible in both host and device modes 1 MFIF Mode...

Page 848: ...modes 30 SESIE Session interrupt enable 0 Disable session interrupt 1 Enable session interrupt Note Accessible in both host and device modes 29 DISCIE Disconnect interrupt enable 0 Disable disconnect interrupt 1 Enable disconnect interrupt Note Only accessible in device mode 28 IDPSCIE ID pin status change interrupt enable 0 Disable connector ID pin status interrupt 1 Enable connector ID pin statu...

Page 849: ... IN transfer not complete interrupt Note Only accessible in device mode 19 OEPIE OUT endpoints interrupt enable 0 Disable OUT endpoints interrupt 1 Enable OUT endpoints interrupt Note Only accessible in device mode 18 IEPIE IN endpoints interrupt enable 0 Disable IN endpoints interrupt 1 Enable IN endpoints interrupt Note Only accessible in device mode 17 16 Reserved Must be kept at reset value 15...

Page 850: ...global non periodic IN NAK effective interrupt 1 Enable global non periodic IN NAK effective interrupt Note Only accessible in device mode 5 NPTXFEIE Non periodic Tx FIFO empty interrupt enable 0 Disable non periodic Tx FIFO empty interrupt 1 Enable non periodic Tx FIFO empty interrupt Note Only accessible in Host mode 4 RXFNEIE Receive FIFO non empty interrupt enable 0 Disable receive FIFO non em...

Page 851: ... only read this register after when Receive FIFO non empty interrupt flag bit of the global interrupt flag register RXFNEIF bit in USBFS_GINTF is triggered This register has to be accessed by word 32 bit Host mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RPCKST 3 0 DPID r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DPID BCOUNT 10 0 CNUM 3 0 r r r Bits Fields Descriptions 31 21 Reserved...

Page 852: ...ptions 31 21 Reserved Must be kept at reset value 20 17 RPCKST 3 0 Received packet status 0001 Global OUT NAK generates an interrupt 0010 OUT data packet received 0011 OUT transfer completed generates an interrupt 0100 SETUP transaction completed generates an interrupt 0110 SETUP data packet received Others Reserved 16 15 DPID 1 0 Data PID The Data PID of the received OUT data packet 00 DATA0 10 D...

Page 853: ...Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 RXFD 15 0 Rx FIFO depth In terms of 32 bit w ords 1 RXFD 1024 Host non periodic transmit FIFO length register Device IN endpoint 0 transmit FIFO length USBFS_HNPTFLEN _DIEP0TFLEN Address offset 0x028 Reset value 0x0200 0200 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HNPTXFD IEP0...

Page 854: ...start address The start address for endpoint0 transmit FIFO RAM is in term of 32 bit w ords Host non periodic transmit FIFO queue status register USBFS_HNPTFQSTAT Address offset 0x002C Reset value 0x0008 0200 This register reports the current status of the non periodic Tx FIFO and request queue The request queue holds IN OUT or other request entries in host mode Note In Device mode this register i...

Page 855: ...request queue 0 Request queue is Full 1 1 entry 2 2 entries n n entries 0 n 8 Others Reserved 15 0 NPTXFS 15 0 Non periodic Tx FIFO space The remaining space of the non periodic transmit FIFO In terms of 32 bit w ords 0 Non periodic Tx FIFO is full 1 1 w ord 2 2 w ords n n w ords 0 n NPTXFD Others Reserved Global core configuration register USBFS_GCCFG Address offset 0x0038 Reset value 0x0000 0000...

Page 856: ...Comparer enable 0 VBUS B device comparer disabled 1 VBUS B device comparer enabled 18 VBUSACEN The VBUS A device Comparer enable 0 VBUS A device comparer disabled 1 VBUS A device comparer enabled 17 Reserved Must be kept at reset value 16 PWRON Pow er on This bit is the pow er sw itch for the internal embedded Full Speed PHY 0 Embedded Full Speed PHY pow er off 1 Embedded Full Speed PHY pow er on ...

Page 857: ... 22 21 20 19 18 17 16 HPTXFD 15 0 r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HPTXFSAR 15 0 r rw Bits Fields Descriptions 31 16 HPTXFD 15 0 Host Periodic Tx FIFO depth In terms of 32 bit w ords 1 HPTXFD 1024 15 0 HPTXFSAR 15 0 Host periodic Tx FIFO RAM start address The start address for host periodic transmit FIFO RAM is in term of 32 bit w ords Device IN endpoint transmit FIFO length register USB...

Page 858: ...FIFO Tx RAM start address The start address for IN endpoint transmit FIFOx is in term of 32 bit w ords 24 7 2 Host control and status registers Host control register USBFS_HCTL Address offset 0x0400 Reset value 0x0000 0000 This register configures the core after power on in host mode Do not modify it after host initialization This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 ...

Page 859: ...7 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FRI 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 FRI 15 0 Frame interval This value describes the frame time in terms of PHY clocks Each time w hen port is enabled after a port reset operation USBFS use a proper value according to the current speed and softw are can w rite to this field to change the value This...

Page 860: ...turns to 0 after it reaches 0x3FFF Host periodic transmit FIFO queue status register USBFS_HPTFQSTAT Address offset 0x0410 Reset value 0x0008 0200 This register reports the current status of the host periodic Tx FIFO and request queue The request queue holds IN OUT or other request entries in host mode This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 861: ...15 0 PTXFS 15 0 Periodic Tx FIFO space The remaining space of the periodic transmit FIFO In terms of 32 bit w ords 0 periodic Tx FIFO is full 1 1 w ord 2 2 w ords n n w ords 0 n PTXFD Others Reserved Host all channels interrupt register USBFS_HACHINT Address offset 0x0414 Reset value 0x0000 0000 When a channel interrupt is triggered USBFS set corresponding bit in this register and software should ...

Page 862: ... in USBFS_GINTF register This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CINTEN 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 CINTEN 7 0 Channel interrupt enable 0 Disable channel n interrupt 1 Enable channel n interrupt Each bit represents a channel Bit 0 for cha...

Page 863: ...eserved 16 13 Reserved Must be kept at reset value 12 PP Port pow er This bit should be set before a port is used Because USBFS doesn t have pow er supply ability it only uses this bit to know w hether the port is in pow ered state Softw are should ensure the true pow er supply on VBUS before setting this bit 0 Port is pow ered off 1 Port is pow ered on 11 10 PLST 1 0 Port line status Report the c...

Page 864: ... Reserved Must be kept at reset value 3 PEDC Port enable disable change Set by the core w hen the status of the Port enable bit 2 in this register changes 2 PE Port Enable This bit is automatically set by USBFS after a USB reset signal finishes and cannot be set by softw are This bit is cleared by the follow ing events A disconnect condition Softw are clearing this bit 0 Port disabled 1 Port enabl...

Page 865: ... are should follow the operation guide to disable or enable a channel 29 ODDFRM Odd frame For periodic transfers interrupt or isochronous transfer this bit controls that w hether in an odd frame or even frame this channel s transaction is desired to be processed 0 Even frame 1 Odd frame 28 22 DAR 6 0 Device address The address of the USB device that this channel w ants to communicate w ith 21 20 R...

Page 866: ...espective channel to know the source of the interrupt The flag bits in this register are all set by hardware and cleared by writing 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DTER REQOVR BBER USBER Reserved ACK NAK STALL Reserved CH TF rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1...

Page 867: ...esponse to other requests during the request processing 0 TF Transfer finished All the transactions of this channel finish successfully and no error occurs For IN channel this flag w ill be triggered after PCNT bits in USBFS_HCHxLEN register reach zero For OUT channel this flag w ill be triggered w hen softw are reads and pops a TF status entry from the RxFIFO Host channel x interrupt enable regis...

Page 868: ...t queue overrun interrupt enable 0 Disable request queue overrun interrupt 1 Enable request queue overrun interrupt 8 BBERIE Babble error interrupt enable 0 Disable babble error interrupt 1 Enable babble error interrupt 7 USBERIE USB bus error interrupt enable 0 Disable USB bus error interrupt 1 Enable USB bus error interrupt 6 Reserved Must be kept at reset value 5 ACKIE ACK interrupt enable 0 Di...

Page 869: ...8 16 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TLEN 15 0 rw Bits Fields Descriptions 31 Reserved Must be kept at reset value 30 29 DPID 1 0 Data PID Softw are should w rite this field before the transfer starts For OUT transfers this field controls the Data PID of the first transmitted packet For IN transfers this field controls the expected Data PID of the first received packet and DTERR w i...

Page 870: ... packet from the RxFIFO this field is decreased by the byte size of the packet 24 7 3 Device control and status registers Device configuration register USBFS_DCFG Address offset 0x0800 Reset value 0x0000 0000 This register configures the core in device mode after power on or after certain control commands or enumeration Do not change this register after device initialization This register has to b...

Page 871: ...w ith a STALL handshake 0 Treat this packet as a normal packet and response according to the status of NAKS and STALL bits in USBFS_DOEPxCTL register 1 Send a STALL handshake and don t save the received OUT packet 1 0 DS 1 0 Device speed This field controls the device speed w hen the device connected to a host 11 Full speed Others Reserved Device control register USBFS_DCTL Address offset 0x0804 R...

Page 872: ...bit again 6 4 Reserved Must be kept at reset value 3 GONS Global OUT NAK status 0 The handshake that USBFS response to OUT transaction packet and w hether to save the OUT data packet are decided by Rx FIFO status endpoint s NAK and STALL bits 1 USHBS alw ays responses to OUT transaction w ith NAK handshake and doesn t save the incoming OUT data packet 2 GINS Global IN NAK status 0 The response to ...

Page 873: ...w ays update this field after receiving a SOF token 7 3 Reserved Must be kept at reset value 2 1 ES 1 0 Enumerated speed This field reports the enumerated device speed Read this field after the ENUMF flag in USBFS_GINTF register is triggered 11 Full speed Others reserved 0 SPST Suspend status This bit reports w hether device is in suspend state 0 Device is not in suspend state 1 Device is in suspe...

Page 874: ...rupt 1 Enable IN endpoint NAK effective interrupt 5 Reserved Must be kept at reset value 4 EPTXFUDEN Endpoint Tx FIFO underrun interrupt enable bit 0 Disable endpoint Tx FIFO underrun interrupt 1 Enable endpoint Tx FIFO underrun interrupt 3 CITOEN Control In timeout interrupt enable bit 0 Disable control In timeout interrupt 1 Enable control In timeout interrupt 2 Reserved Must be kept at reset va...

Page 875: ...t at reset value 6 BTBSTPEN Back to back SETUP packets Only for control OUT endpoint interrupt enable bit 0 Disable back to back SETUP packets interrupt 1 Enable back to back SETUP packets interrupt 5 Reserved Must be kept at reset value 4 EPRXFOVREN Endpoint Rx FIFO overrun interrupt enable bit 0 Disable endpoint Rx FIFO overrun interrupt 1 Enable endpoint Rx FIFO overrun interrupt 3 STPFEN SETUP...

Page 876: ...pt at reset value 19 16 OEPITB 3 0 Device all OUT endpoint interrupt bits Each bit represents an OUT endpoint Bit 16 for OUT endpoint 0 bit 19 for OUT endpoint 3 15 4 Reserved Must be kept at reset value 3 0 IEPITB 3 0 Device all IN endpoint interrupt bits Each bit represents an IN endpoint Bit 0 for IN endpoint 0 bit 3 for IN endpoint 3 Device all endpoints interrupt enable register USBFS_DAEPINT...

Page 877: ...esents an OUT endpoint Bit 16 for OUT endpoint 0 bit 19 for OUT endpoint 3 15 4 Reserved Must be kept at reset value 3 0 IEPIE 3 0 IN endpoint interrupt enable bits 0 Disable IN endpoint n interrupt 1 Enable IN endpoint n interrupt Each bit represents an IN endpoint Bit 0 for IN endpoint 0 bit 3 for IN endpoint 3 Device VBUS discharge time register USBFS_DVBUSDT Address offset 0x0828 Reset value 0...

Page 878: ...USBFS_DVBUSPT Address offset 0x082C Reset value 0x0000 05B8 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DVBUSPT 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 DVBUSPT 11 0 Device VBUS pulsing time This field defines the pulsing time for VBUS The true pulsing...

Page 879: ...s This field controls w hether the TXFE bits in USBFS_DIEPxINTF registers are able to generate an endpoint interrupt bit in USBFS_DAEPINT register Bit 0 for IN endpoint 0 bit 3 for IN endpoint 3 0 Disable FIFO empty interrupt 1 Enable FIFO empty interrupt Device IN endpoint 0 control register USBFS_DIEP0CTL Address offset 0x0900 Reset value 0x0000 8000 This register has to be accessed by word 32 b...

Page 880: ...ndshake w hen receiving IN token USBFS w ill clear this bit after a SETUP token is received on the corresponding OUT endpoint 0 This bit has a higher priority than NAKS bit in this register and GINS bit in USBFS_DCTL register If both STALL and NAKS bits are set the STALL bit takes effect 20 Reserved Must be kept at reset value 19 18 EPTYPE 1 0 Endpoint type This field is fixed to 00 for control en...

Page 881: ...rved EPTYPE 1 0 NAKS EOFRM DPID rs rs w w w w rw rw rs rw r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EPACT Reserved MPL 10 0 rw rw Bits Fields Descriptions 31 EPEN Endpoint enable Set by the application and cleared by USBFS 0 Endpoint disabled 1 Endpoint enabled Softw are should follow the operation guide to disable or enable an endpoint 30 EPD Endpoint disable Softw are can set this bit to disable...

Page 882: ... token is received on the corresponding OUT endpoint Softw are is not able to clear it For interrupt or bulk IN endpoint Only softw are can clear this bit 20 Reserved Must be kept at reset value 19 18 EPTYPE 1 0 Endpoint type This field defines the transfer type of this endpoint 00 Control 01 Isochronous 10 Bulk 11 Interrupt 17 NAKS NAK status This bit controls the NAK status of USBFS w hen both S...

Page 883: ...sn t make any response 14 11 Reserved Must be kept at reset value 10 0 MPL 10 0 This field defines the maximum packet length in bytes Device OUT endpoint 0 control register USBFS_DOEP0CTL Address offset 0x0B00 Reset value 0x0000 8000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EPEN EPD Reserved SNAK CNAK Reserved STALL SNOOP EPTYPE 1 0 NAKS Reser...

Page 884: ...eck the received data packet s CRC value 0 Snoop mode disabled 1 Snoop mode enabled 19 18 EPTYPE 1 0 Endpoint type This field is fixed to 00 for control endpoint 17 NAKS NAK status This bit controls the NAK status of USBFS w hen both STALL bit in this register and GONS bit in USBFS_DCTL register are cleared 0 USBFS sends data or handshake packets according to the status of the endpoint s Rx FIFO 1...

Page 885: ...he application and cleared by USBFS 0 Endpoint disabled 1 Endpoint enabled Softw are should follow the operation guide to disable or enable an endpoint 30 EPD Endpoint disable Softw are can set this bit to disable the endpoint Softw are should follow the operation guide to disable or enable an endpoint 29 SODDFRM SD1PID Set odd frame For isochronous OUT endpoints This bit has effect only if this i...

Page 886: ...t check the received data packet s CRC value 0 Snoop mode disabled 1 Snoop mode enabled 19 18 EPTYPE 1 0 Endpoint type This field defines the transfer type of this endpoint 00 Control 01 Isochronous 10 Bulk 11 Interrupt 17 NAKS NAK status This bit controls the NAK status of USBFS w hen both STALL bit in this register and GONS bit in USBFS_DCTL register are cleared 0 USBFS sends handshake packets a...

Page 887: ...e x endpoint_number Address offset 0x0908 endpoint_number 0x20 Reset value 0x0000 0080 This register contains the status and events of an IN endpoint when an IN endpoint interrupt occurs read this register for the respective endpoint to know the source of the interrupt The flag bits in this register are all set by hardware and cleared by writing 1 except the read only TXFE bit This register has to...

Page 888: ... Transfer finished This flag is triggered w hen all the IN transactions assigned to this endpoint have been finished Device OUT endpoint x interrupt flag register USBFS_DOEPxINTF x 0 3 where x endpoint_number Address offset 0x0B08 endpoint_number 0x20 Reset value 0x0000 0000 This register contains the status and events of an OUT endpoint when an OUT endpoint interrupt occurs read this register for...

Page 889: ...riggered w hen a setup phase finished i e USBFS receives an IN or OUT token after a setup token 2 Reserved Must be kept at reset value 1 EPDIS Endpoint disabled This flag is triggered w hen an endpoint is disabled by the softw are s request 0 TF Transfer finished This flag is triggered w hen all the OUT transactions assigned to this endpoint have been finished Device IN endpoint 0 transfer length ...

Page 890: ...ield is decreased by the byte size of the packet Device OUT endpoint 0 transfer length register USBFS_DOEP0LEN Address offset 0x0B10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved STPCNT 1 0 Reserved PCNT Reserved rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TLEN 6 0 rw Bits Fields Descriptions 31 Reserved Mu...

Page 891: ...t is enabled Each time softw are reads out a packet from the Rx FIFO this field is decreased by the byte size of the packet Device IN endpoint x transfer length register USBFS_DIEPxLEN x 1 3 where x endpoint_number Address offset 0x910 endpoint_number 0x20 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved MCPF 1 0 PCNT ...

Page 892: ...ully w rites a packet into the endpoint s Tx FIFO this field is decreased by the byte size of the packet Device OUT endpoint x transfer length register USBFS_DOEPxLEN x 1 3 where x endpoint_number Address offset 0x0B10 endpoint_number 0x20 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RXDPID STPCN T 1 0 PCNT 9 0 TLE...

Page 893: ...ly by USBFS after each successfuldata packet reception on bus 18 0 TLEN 18 0 Transfer length The total data bytes number of a transfer This field is the total data bytes of all the data packets desired to receive in an OUT transfer Program this field before the endpoint is enabled Each time after software reads out a packet from the RxFIFO this field is decreased by the byte size of the packet Dev...

Page 894: ...r USBFS_PWRCLKCTL Address offset 0x0E00 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SHCLK SUCLK rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 SHCLK Stop HCLK Stop the HCLK to save pow er 0 HCLK is not stopped 1 HCLK is stopped 0 SUCLK Stop...

Page 895: ... FIFO FIFO controller window timing embedded sync detection DMA interface and control register Figure 25 1 DCI module block diagram HS VS Control Register Pixel FIFO FIFO Controler Window Timing Embedded Sync Detection Signal Processing PIX_DATA 13 0 AHB Interface DMA Request DMA Interface DCI_PixClk DCI_PixData 13 0 DCI_Hs DCI_Vs The signal processing module generates useful signals for other int...

Page 896: ...e between DCI and software 25 4 Signal description Table 25 1 PINsused by DCI Direction Name Width Description Input DCI_PixClk 1 DCI Pixel Clock Input DCI_PixData 14 DCI Pixel Data Input DCI_Hs 1 DCI Horizontal Synchronization Input DCI_Vs 1 DCI Vertical Synchronization 25 5 Function overview 25 5 1 DCI hardware synchronization mode In DCI hardware synchronization mode ESM bit in DCI_CTL register...

Page 897: ...dded synchronization mode the 0xFF and 0x00 should not appear in pixel data to avoid mistake In embedded synchronization mode DCI starts to detect the sync codes after enabled and recover line frame synchronization information For example DCI starts to capture a new frame if it detects a Frame End codeand then a Frame Start Code When detecting sync code it is possible to make DCI compare only a fe...

Page 898: ...rame flag will be triggered and DCI stops the capture 25 5 5 Pixel formats data padding and DMA DCI supports various pixel digital encoding formats including YCbCr422 RGB565 However DCI only receives these pixel data pads these pixels into a word and push into a pixel FIFO DCI doesn t perform any pixel format conversion or data processing and doesn t care about the detail of pixel format DCI uses ...

Page 899: ... 25 3 Memory view in half word padding mode 2 b00 D1 13 0 2 b00 D0 13 0 2 b00 D3 13 0 2 b00 D2 13 0 2 b00 D5 13 0 2 b00 D4 13 0 2 b00 D7 13 0 2 b00 D6 13 0 25 6 Interrupts There are several status and error flags in DCI and interrupts may be asserted from these flags These status and error flags will assert global DCI interrupt if enabled by corresponding bit in DCI_INTEN These flags are cleared b...

Page 900: ...tions 31 15 Reserved Must be kept at reset value 14 DCIEN DCI Enable 0 DCI is disabled 1 DCI is enabled 13 12 Reserved Must be kept at reset value 11 10 DCIF 1 0 Digital Camera Interface Format 00 8 bit data on every pixel clock 01 10 bit data on every pixel clock 10 12 bit data on every pixel clock 11 14 bit data on every pixel clock 9 8 FR 1 0 Frame Rate FR defines the frame capture rate in cont...

Page 901: ... 1 Window is enabled 1 SNAP Snapshot Mode 0 Continuous capture mode 1 Snapshot capture mode 0 CAP Capture Enable 0 Frame not captured 1 Frame is captured 25 7 2 Status register0 DCI_STAT0 Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FV VS HS r r r B...

Page 902: ...8 7 6 5 4 3 2 1 0 Reserved ELF VSF ESEF OVRF EFF r r r r r Bits Fields Descriptions 31 5 Reserved Must be kept at reset value 4 ELF End of Line Flag 0 No end of line flag 1 A line is captured by DCI 3 VSF Vsync Flag 0 No vsync flag 1 A vsync blanking detected 2 ESEF Embedded Synchronous Error Flag 0 No Embedded Synchronous Error Flag 1 A Embedded Synchronous Error detected 1 OVRF FIFO Overrun Flag...

Page 903: ...g w illgenerate interrupt 2 ESEIE Embedded Synchronous Error Interrupt Enable 0 Embedded Synchronous Error Flag w on t generate interrupt 1 Embedded Synchronous Error Flag w ill generate interrupt 1 OVRIE FIFO Overrun Interrupt Enable 0 FIFO Overrun w on t generate interrupt 1 FIFO Overrun w ill generate interrupt 0 EFIE End of Frame Interrupt Enable 0 End of frame flag w on t generate interrupt 1...

Page 904: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ELFC VSFC ESEFC OVRFC EFFC w w w w w Bits Fields Descriptions 31 5 Reserved Must be kept at reset value 4 ELFC End of Line Flag Clear Write 1 to clear end of line flag 3 VSFC Vsync flag clear Write 1 to clear vsync flag 2 ESEFC Clear embedded synchronous Error Flag Write 1 to clear Embedded Synch...

Page 905: ...7 8 Synchronization codes unmask register DCI_SCUMSK Address offset 0x1C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FEM 7 0 LEM 7 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSM 7 0 FSM 7 0 rw rw Bits Fields Descriptions 31 24 FEM 7 0 Frame End Code unMask Bits in Embedded Synchronous Mode 23 16 LEM 7 0 Line End Code un...

Page 906: ... WHSP 13 0 Window Horizontal Start Position Zero means the first pixel in a line 25 7 10 Cropping window size register DCI_CWSZ Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved WVSZ 13 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WHSZ 13 0 rw Bits Fields Descriptions 31 30 Reserved Must be ke...

Page 907: ...his register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DT3 7 0 DT2 7 0 r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DT1 7 0 DT0 7 0 r r Bits Fields Descriptions 31 24 DT3 7 0 Pixel Data 3 23 16 DT2 7 0 Pixel Data 2 15 8 DT1 7 0 Pixel Data 1 7 0 DT0 7 0 Pixel Data 0 ...

Page 908: ... configurable for capacitive sensing Channel Pins and 3 for Sample Pins Configurable transfer sequence frequency Able to implement the user specific charge transfer sequences Sequence end and error flags configurable interrupts Spread spectrum function implemented 26 3 Function Overview 26 3 1 TSI block diagram Figure 26 1 Block diagram of TSI module TSI registers AHB Bus Group 0 IO Controller Pul...

Page 909: ...is achannel pinandPIN1is asamplepinwhilePIN2andPIN3 are unused An electrode connecting PIN0 is designed on PCB board The A sample capacitor Cs connected to sample pin PIN1 is also required Now the capacitance of the channel pin PIN0 includes Cx and the capacitance introduced by the electrode so capacitance of PIN0 increases when a finger is touching while the capacitance of PIN1 remains unchanged ...

Page 910: ... software before starting a charge transfer sequence Discharging time in this step should be guaranteed to ensure that the voltage of Cx and Cs are discharged to zero 2 Buffer Time1 Buffer time withASW_0 andASW_1 open PIN0 is configured to input floating 3 Charge Channel pin PIN0 is configured to output high in order to charge Cx ASW_0 and ASW_1 remain open during this step The charging time shoul...

Page 911: ...n Vs is zero after initial step and increases after each charge cycle as shown in Figure 26 3 Voltage of a sample pin during charge transfer sequence A larger Cx will cause a greater increase during a cycle The sequence stops when Vs reaches Vth Each group has a counter which records the number of cycles performed on it toreach Vth At theendofcharge transfersequence thegroupcounteris readout toest...

Page 912: ...rge transfer sequence The FSM leaves a state if the duration time of this state reaches defined value and goes into the next state The ExtendChargestateis present only iftheECENbit is set inTSI_CTL0 register This state is designedtoimplement spread spectrum function whichwill extendthedurationofthepulse highstatewithdifferent extendtimeaccordingtocurrent FSM cyclenumber Soinotherword the charge fr...

Page 913: ...he duration time of each state except Extend Charge state is fixed in each loop according to the configuration of the register The durationtimeof BufferTime1 BufferTime2and BufferTime3are fixedto2 HCLK periods The duration time of Charge state and Charge Transfer state is defined by CDT and CTDT bits see TSI_CTL0 register section for detail Generally thevariationrange of extendchargefrequency is l...

Page 914: ...echarge transferFSM take control of these channels or sample pins mode and the states of related analog switches when the sequence is on going When the sequence is in IDLE state PINMOD bit in TSI_CTL0 register defines the mode of these pins Pins that are configured in GPIO used by TSI but neither sample nor channel in TSI register is called free pins whose mode is defined by PINMOD bit in TSI_CTL0...

Page 915: ...TSI is started by falling rising edge on the trigger pin Wait for the CTCF or MNERR flag in TSI_INTF and clear these flags by writing TSI_INTC Read out the CYCN bits in TSI_GxCYCN registers 26 3 9 TSI flags and interrupts Table 26 4 TSI errorsand flags Flag Name Description Cleared by CTCF TSI stops because all enabled samplers sample pins reach Vth CCTCF bit in TSI_INTC MNERR TSI stops because th...

Page 916: ... CDT 3 0 is set and clear by softw are These bits controls the duration time of Charge State in a charge transfer sequence 0000 1 tCTCLK 0001 2 tCTCLK 0010 3 tCTCLK 1111 16 tCTCLK 27 24 CTDT 3 0 Charge Transfer State Duration Time CTDT 3 0 is set and clear by softw are These bits control the duration time of Charge Transfer State in a charge transfer sequence 0000 1 tCTCLK 0001 2 tCTCLK 0010 3 tCT...

Page 917: ...TSI_CTL0 14 12 CTCDIV 2 0 Charge Transfer clock CTCLK division factor CTCLK in TSI is divided from HCLK and CTCDIV defines the division factor 0000 fCTCLK fHCLK 0001 fCTCLK fHCLK 2 0010 fCTCLK fHCLK 4 0011 fCTCLK fHCLK 8 0111 fCTCLK fHCLK 128 1000 fCTCLK fHCLK 256 1001 fCTCLK fHCLK 512 1110 fCTCLK fHCLK 16384 1111 fCTCLK fHCLK 32768 Note CTCDIV 3 is located in TSI_CTL1 and CTCDIV 2 0 are located i...

Page 918: ...1 TSIS TSI start This bit is set by softw are to start a charge transfer sequence in softw are trigger mode and reset by hardw are w hen the sequence stops After setting this bit softw are can reset it to stop the started sequence manually 0 TSI is not started 1 TSI is started 0 TSIEN TSI enable 0 TSI module is enabled 1 TSI module is disabled 26 4 2 Interrupt enable register TSI_INTEN Address off...

Page 919: ...6 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CMNERR CCTCF w w Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 CMNERR Clear max cycle number error 0 Reserved 1 Clear MNERR 0 CCTCF Clear charge transfer complete flag 0 Reserved 1 Clear CTCF 26 4 4 Interrupt flag register TSI_INTF Address offset 0x0C Reset value 0x0000 0000 This register...

Page 920: ...N 2 0 This bit is cleared by w riting 1 to CCTCF bit in TSI_ICR register 0 Charge Transfer not complete 1 Charge Transfer complete 26 4 5 Pin hysteresis mode register TSI_PHM Address offset 0x10 Reset value 0xFFFF FFFF This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved G2P3 G2P2 G2P1 G2P0 G1P3 G1P2 G1...

Page 921: ...losed 26 4 7 Sample configuration register TSI_SAMPCFG Address offset 0x20 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved G2P3 G2P2 G2P1 G2P0 G1P3 G1P2 G1P1 G1P0 G0P3 G0P2 G0P1 G0P0 rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 12 Reserved Must be kept at ...

Page 922: ... 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved GC2 GC1 GC0 r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved GE2 GE1 GE0 rw rw rw Bits Fields Descriptions 31 19 Reserved Must be kept at reset value 18 16 GCx Group complete This bit is set by hardw are w hen charge transfer sequence for an enabled group is complete It is cleared...

Page 923: ... soon as a charge transfer sequence completes They are cleared by hardw are w hen a new charge transfer sequence starts 26 4 11 Control register1 TSI_CTL1 Address offset 0x300 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved ECDIV 2 1 Reserved CTCDIV 3 Reserved rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits Fie...

Page 924: ...24 CTCDIV 3 Charge Transfer clock CTCLK division factor CTCLK in TSI is divided from HCLK and CTCDIV defines the division factor 0000 fCTCLK fHCLK 0001 fCTCLK fHCLK 2 0010 fCTCLK fHCLK 4 0011 fCTCLK fHCLK 8 0111 fCTCLK fHCLK 128 1000 fCTCLK fHCLK 256 1001 fCTCLK fHCLK 512 1110 fCTCLK fHCLK 16384 1111 fCTCLK fHCLK 32768 Note CTCDIV 3 is located in TSI_CTL1 and CTCDIV 2 0 are located in TSI_CTL0 23 ...

Page 925: ...transfer is supported and data can be accessed in the input and output FIFO 27 2 Characteristics DES TDES and AES encryption decryption algorithms are supported Multiple modes are supported respectively in DES TDES and AES including Electronic codebook ECB Cipher block chaining CBC Counter mode CTR Galois counter mode GCM Galois message authentication code mode GMAC Counter with CBC MAC CCM Cipher...

Page 926: ...ssor The same swapping operation should be also performed on the processor output data before they are collected Note the least significant data always occupies the lowest address location no matter which data type is configured because the system memory is little endian Figure 27 1 DATAM No swapping and Half word swapping and Figure 27 2 DATAM Byte swapping and Bit swapping illustrate the128 bit ...

Page 927: ...CTR GCM GMAC CCM CFB and OFB modes to XOR with data blocks They are independent of plaintext and ciphertext and the DATAM value will not affect them Note the initialization vector registers CAU_IV0 1 H L can only be written when BUSY is 0 otherwise the write operations are invalid 27 4 Cryptographic acceleration processor The cryptographic acceleration unit implements DES and AES acceleration proc...

Page 928: ...thm is configured three different keying options are allowed 1 Three same keys The three keys KEY3 KEY2 and KEY1 are completely equal which means KEY3 KEY2 KEY1 FIPS PUB 46 3 1999 and ANSI X9 52 1998 refers to this option It is easy to understand that this mode is equivalent to DES 2 Two different keys In this option KEY2 is different from KEY1 and KEY3 is equal to KEY1 which means KEY1 and KEY2 a...

Page 929: ...trated in Figure 27 4 DES TDES ECB encryption Figure 27 4 DES TDES ECB encryption SWAP CAU_DI DATAM DEA encrypt DEA encrypt DEA decrypt KEY1 KEY2 KEY3 SWAP CAU_DO Plaintext Ciphertext DES TDES ECB decryption The 64 bit input ciphertext is first obtained after data swapping according to the data type WhentheTDES algorithm is configured theinput datablockis readintheDEA anddecrypted using KEY3 The o...

Page 930: ...hen decrypted using KEY2 After that the output is fed back directly to the last DEA and encrypted with KEY3 The result is then used as the next initialization vector and exclusive ORed with the next plaintext data block to process next encryption Theabove operations are repeateduntil thelast plaintext blockis encrypted Note if the plaintext message does not consist of an integral number of data bl...

Page 931: ... XORed with the initialization vector which is the same as that used during encryption At the same time the first ciphertext is then used as the next initialization vector and exclusive ORed with the next result after DEA blocks The above operations are repeated until the last ciphertext block is decrypted Note if the ciphertext message does not consist of an integral number of data blocks the fin...

Page 932: ... KEY3 KEY2 when the key size is configured as 128 KEY3 KEY2 KEY1 when the key size is configured as 192 and KEY3 KEY2 KEY1 KEY0 when the key size is configured as 256 The thorough explanationofthekey usedintheAES is providedin FIPS PUB 197 November 26 2001 and the explanation process is omitted in this manual AES ECB mode encryption The 128 bit input plaintext is first obtained after data swapping...

Page 933: ...ration is then used as the first round key in the decryption After the key derivation the 128 bit input ciphertext is first obtained after data swapping according to the data type The input data block is read in the AEA and decrypted using keys prepared above The output is then swapped back according to the data type again and a 128 bit plaintext is produced The procedure of AES ECB mode decryptio...

Page 934: ... 27 10 AES CBC encryption SWAP CAU_DI DATAM AEA encrypt CAU_KEY0 3 SWAP CAU_DO Plaintext Ciphertext CAU_IV0 1 H L AES CBC mode decryption Similar to that in AES ECB mode decryption the key derivation also must be completed first to prepare the decryption keys the input of the key schedule should be the same to that used in encryption The last round key obtained from the above operation is then use...

Page 935: ...in encryption and decryption the key schedules during the encryption and decryption are the same Then decryption operation acts exactly in the same way as the encryption operation Only the 32 bit LSB of the 128 bit initialization vector represents the counter which means the other 96 bits are unchanged during the operation and the initial value should be set to 1 Nonceis 32 bit single userandom va...

Page 936: ...lated and saved internally to be used later a Clear the CAUEN bit to make sure CAU is disabled b Configure the ALGM 3 0 bits to 1000 c Configure GCM_CCMPH 1 0 bits to 00 d Configure key registers and initialization vectors e Enable CAU by writing 1 to CAUEN bit f Wait until CAUEN bit is cleared by hardware and then enable CAU again for following phases 2 GCM AAD additional authenticated data phase...

Page 937: ...tication tag q Disable the CAU Note The key should be prepared at the beginning when a decryption is performed AES GMAC mode The AES Galois message authentication code mode is also supported to authenticate the message It is processing based on the AES GCM mode while the encryption decryption phase is by passed AES CCM mode The AES combined cipher machine mode which is similar to AES GCM mode also...

Page 938: ...eceive data The sizeof the AADmust bea multipleof128 bits DMA can also be used j Repeat i until all AAD data are supplied wait until BUSY bit is cleared 3 CCM encryption decryption phase This phase must be performed after CCM AAD phase In this phase the message is authenticated and encrypted decrypted Like GCM the CCM chaining mode can be applied on a message composed only by plaintext authenticat...

Page 939: ...KEYM bits in the CAU_CTL register if AES algorithm is chosen 3 Configure the CAU_KEY0 3 H L registers according tothe algorithm 4 Configure the DATAM bit in the CAU_CTL register to select thedata swapping type 5 Configure the algorithm DES TDES AES and the chaining mode ECB CBC CTR GCM GMAC CCM CFB OFB by writing the ALGM 3 0 bit in the CAU_CTL register 6 Configure the encryption direction by writ...

Page 940: ...ts noDMAorinterrupts 14 Wait for ONE bit in the CAU_STAT0 register is 1 then read the CAU_DO registers The output data can also be transferred by DMA CPU during interrupts no DMA or interrupts 15 Repeat steps 13 14 until all data blocks has been decrypted 27 6 CAU DMA interface The DMA can be used to transfer data blocks with the interface of the cryptographic acceleration unit The operations can ...

Page 941: ...DMAIEN bit in the CAU_DMAEN register 2 When it is DES or AES wait until both the input and output FIFO are both empty if the input FIFO is not empty IEM 0 then write a word of data into CAU_DI register do as so until the IEM is checked to be 1 then wait until the BUSY bit is cleared so that the next data block will not be affected by the last one Case of TDES is similar to that of AES except that ...

Page 942: ...ation mode direction GCM CCM phase and the key values When it is CBC CTR GCM GMAC CCM CFB or OFB chaining mode the initialization vectors should also be stored When it is GCM GMAC or CCM mode the context switch registers CAU_GCMCCMCTXSx x 0 7 and CAU_GCMCTXSx x 0 7 should also be stored 4 Configure and process the new data block 5 Restore the process before Configure the CAU with the parameters st...

Page 943: ...ons 31 20 Reserved Must be kept at reset value 19 ALGM 3 Encryption decryption algorithm mode bit 3 18 Reserved Must be kept at reset value 17 16 GCM_CCMPH 1 0 GCM CCM phase 00 prepare phase 01 AAD phase 10 encryption decryption phase 11 tag phase 15 CAUEN CAU Enable 0 CAU is disabled 1 CAU is enabled Note the CAUEN can be cleared automatically w hen the key derivation ALGM 0111b is finished or th...

Page 944: ...w ith data blocks 0100 AES ECB w ith CAU_KEY0 1 2 3 Initialization vectors CAU_IV0 1 are not used 0101 AES CBC w ith CAU_KEY0 1 2 3 Initialization vectors CAU_IV0 1 are used to XOR w ith data blocks 0110 AES_CTR w ith CAU_KEY0 1 2 3 Initialization vectors CAU_IV0 1 are used to XOR w ith data blocks In this mode encryption and decryption are same then the CAUDIR is disregarded 0111 AES key derivati...

Page 945: ...full 0 Output FIFO is not full 1 Output FIFO is full 2 ONE Output FIFO is not empty 0 Output FIFO is empty 1 Output FIFO is not empty 1 INF Input FIFO is not full 0 Input FIFO is full 1 Input FIFO is not full 0 IEM Input FIFO is empty 0 Input FIFO is not empty 1 Input FIFO is empty 27 9 3 Data input register CAU_DI Address offset 0x08 Reset value 0x0000 0000 The data input register is used to tran...

Page 946: ...000 The data output register is a read only register It is used to receive plaintext or ciphertext results from theoutput FIFO SimilartoCAU_DI theMSB is readat first while theLSB is read at last This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DO 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DO 15 0 r Bits Fields Descriptions 31 0 DO 31 0 Data output ...

Page 947: ...e register CAU_INTEN Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OINTEN IINTEN rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 OINTEN OUT FIFO interrupt enable 0 OUT FIFO interrupt is disable 1 OUT FIFO interrupt is enabl...

Page 948: ...0 IN FIFO interrupt not pending 1 IN FIFO interrupt flag pending 27 9 8 Interrupt flag register CAU_INTF Address offset 0x1C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OINTF IINTF r r Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 OINTF OUT FIFO...

Page 949: ...KEY 64 127 and KEY3H 31 0 KEY3L 31 0 is used as AES_KEY 128 191 In AES 256 mode KEY0H 31 0 KEY0L 31 0 is used as AES_KEY 0 63 KEY1H 31 0 KEY1L 31 0 is used as AES_KEY 64 127 KEY2H 31 0 KEY2L 31 0 is used as AES_KEY 128 191 and KEY3H 31 0 KEY3L 31 0 is used as AES_KEY 192 255 NOTE is a concatenation operator For example X Y denotes the concatenation of two bit strings Xand Y CAU_KEY0H Address offse...

Page 950: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY1L 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY1L 15 0 w CAU_KEY2H Address offset 0x30 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY2H 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY2H 15 0 w CAU_KEY2L Address offset 0x34 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY2L 31 16 w 15 ...

Page 951: ...w Bits Fields Descriptions 31 0 KEY0 3 H L The key for DES TDES AES 27 9 10 Initial vector registers CAU_IV0 1 H L Address offset 0x40 to 0x4C Reset value 0x0000 0000 This registers have to be accessed by word 32 bit and all of them must be written when BUSY is 0 In DES TDES mode IV0His theleftmostbits andIV0Lis therightmostbits oftheinitialization vectors In AES mode IV0H is the leftmost bits and...

Page 952: ... 3 2 1 0 IV0L 15 0 rw CAU_IV1H Address offset 0x48 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IV1H 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV1H 15 0 rw CAU_IV1L Address offset 0x4C Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IV1L 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV1L 15 0 rw Bits Fields Descriptions 31 0 IV0 1 H L The in...

Page 953: ...e registers to resume the suspended processing Note These registers are used only w hen GCM GMAC or CCM mode is selected 27 9 12 GCM mode context switch register x CAU_GCMCTXSx x 0 7 Address offset 0x70 to 0x8C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CTXx 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTXx 15 0 rw Bits...

Page 954: ... peripheral High performance of computation of hash algorithms Little endian data representation Multiple data types are supported including no swapping half word swapping byte swapping and bit swapping with 32 bit data words Automatic data padding to fill the 512 bit message block for digest computation DMA transfer is supported Hash HMAC process suspended mode 28 3 HAU data type The hash acceler...

Page 955: ...swapping WORD 0 MSB WORD 1 WORD 2 WORD 3 LSB WORD 0 MSB WORD 1 WORD 2 WORD 3 LSB Figure 28 2 DATAM Byte swapping and Bit swapping Byte swapping A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 D3 D2 D1 D0 A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3 D0 D1 D2 D3 WORD 0 MSB Bit swapping A31 A1 A0 B31 B1 B0 C31 C1 C0 D31 D1 D0 A0 A1 A31 B0 B1 B31 C0 C1 C31 D0 D1 D31 WORD 1 WORD 2 WORD 3 LSB WORD 0 MSB WORD 1 WORD 2 WORD 3...

Page 956: ... usingthe digest is computationally impossible and the result will be completely different with any change to the input message Figure 28 3 HAU block diagram AHB BUS Input FIFO 16 32 HAU_DI HAU_DO Data swapping Config Hash acceleration core SHA 1 SHA 224 SHA 256 MD5 Hash HMAC HAU_CTL HAU_STAT HAU_CFG HAU_INTEN 28 4 1 Automatic data padding The input message should be padded first so that the numbe...

Page 957: ...en into the HAU core by DMA or CPU To start the processing of the HAU core the peripheral must obtain the information as to whether the HAU_DI register contains the last bits of the message or not This can be confirmed with the status of the input FIFO and the HAU_DI register When DMA is used to transfer data The status of the block transfer is automatically interpreted with the information from t...

Page 958: ...g for message authentication H Krawczyk M Bellare R Canetti February 1997 The HMAC algorithm can be represented as HMAC input HASH key opad XOR 0x5c HASH key ipad XOR 0x36 input where ipad and opad are used to extend the key to 512 bits with several 0 and is the concatenation operator There are four different phases in the HMAC mode 1 Configure the HMS bit in the HAU_CTL register as 1 and set the ...

Page 959: ...sters to memory 3 Configure and process the new message 4 Restore the process before Restore the content from memory to HAU_INTEN HAU_CFG and HAU_CTL registers 5 Resume the message calculation Set START bit of HAU_CTL register to 1 to restart a new message digest calculation 6 Resume the previous core state Restore the content from memory to HAU_CTXS0 HAU_CTXS37 HAU_CTXS0 HAU_CTXS53 when HMAC oper...

Page 960: ...ompletely processed and the next block has not been pushed into input FIFO so there is no need to save and restore HAU_CTXS22 HAU_CTXS37 registers 28 6 HAU interrupt There are two types of interrupt registers in HAU which are both in HAU_STAT register In HAU the interrupt is used to indicate the situation of the input FIFOand the status of whether the digest calculation is completed Any of interru...

Page 961: ...ed Must be kept at reset value 16 KLM Key length mode 0 Key length 64 bytes 1 Key length 64 bytes Note This bit must be changed w hen no computation is processing 15 14 Reserved Must be kept at reset value 13 MDS Multiple DMA Selection Set this bit if hash message is large files and multiple DMA transfers are needed 0 Single DMA transfers needed and CALEN bit is automatically set at the end of a D...

Page 962: ...w apping The data w ritten into HAU_DI need half w ord sw apping before w rite to FIFO 10 Bytes sw apping The data w ritten into HAU_DI need bytes sw apping before w rite to FIFO 11 Bit sw apping The data w ritten into HAU_DI need bytes sw apping before w rite to FIFO 3 DMAE DMA enable 0 DMA disabled 1 DMA enabled Note 1 This bit is cleared w hen transferring the last data of the message but not c...

Page 963: ...0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CALEN Reserved VBL 4 0 w rw Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 CALEN Digest calculation enable 0 No calculation 1 Start data padding w ith VBL prepared previously Start the calculation of the last digest ...

Page 964: ...are used to receive results from the output FIFO And they are reset by the START bit Any read access when calculating will be extended until the calculation is completed In SHA 1 mode HAU_DO0 4 are used In MD5 mode HAU_DO0 3 are used In SHA 224 mode HAU_DO0 6 are used In SHA 256 mode HAU_DO0 7 are used HAU_DO0 Address offset 0x0C and 0x310 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DO0 31 16 ...

Page 965: ...1 10 9 8 7 6 5 4 3 2 1 0 DO3 15 0 r HAU_DO4 Address offset 0x1C and 0x320 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DO4 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DO4 15 0 r HAU_DO5 Address offset 0x324 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DO5 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DO5 15 0 r HAU_DO6 Address offset 0x328 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DO...

Page 966: ...ter has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CCIE DIIE rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 CCIE Calculation completion interrupt enable 0 Calculation completion interrupt is disabled 1 Calculation completion interrupt is enabled 0 DIIE Data input interrupt enable ...

Page 967: ...d 1 Digest calculation is completed 0 DIF Data input flag 0 A data is w ritten to data input register 1 A data processing is completed only the data in input FIFO w ill be processed 28 7 7 Context switch register x HAU_CTXSx x 0 53 Address offset 0xF8 0x04 x x 0 53 Reset value 0x0000 0002 when x 0 0x0000 0000 when x 1 to 53 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23...

Page 968: ... exponentiation RSA CRT exponentiation ECC scalar multiplication check point on elliptic curve ECDSA Elliptic Curve Digital Signature Algorithm signature and verification Support Montgomery multiplication accelerate RSA DH and ECC operations Embedded RAM of 3584 bytes Conversion between the Montgomery domain and the natural domain PKCAU is a 32 bit peripheral only 32 bit access is supported 29 3 F...

Page 969: ... algorithm with up to 640 bits 20 words of operands The maximum ROS is 99 words and the maximum EOS is 21 words When writing the input parameters to the PKCAU RAM a word 0x00000000 must be added The PKCAU RAM is little endian For example when writing the input parameter xp of ECC P256 for ECC scalar multiplication to PKCAU RAM the modulus length is 8 words address offset 0x55C stores the lowest by...

Page 970: ...ulate L n p 1 q 1 n is euler function 4 Select e 1 e L e and L must be relatively prime 5 Calculate d 1 d L and e d mod L 1 The parameters show in Table 29 1 Parametersof RSA algorithm can be obtained by the above calculation Table 29 1 Parametersof RSA algorithm Parameters Description n modulus e public exponent d private exponent n e public key n d private key RSA encryption Bob generates a key ...

Page 971: ...e order n The hash function is HASH z is the Ln leftmost bits of HASH M where Ln is the bit length of the order n The ECDSA sign and verification are detailed as follows ECDSA sign The signatureresult of ECDSAconsistsofr ands Theprocess togenerateECDSAsignature is shown in Figure 29 3 Flow chart of ECDSA sign Figure 29 3 Flow chart of ECDSA sign Select random number k 0 k n Calculate R k x G Calcu...

Page 972: ...te P u1 G u2 Q Invalid signature r xP mod n xP is the x coordinate of P No Valid signature Yes 0 r n and 0 s n Yes No start finish Note The HASH in the above diagram is the agreed cryptographic hash function 29 3 4 Integer arithmetic operations The integer arithmetic operation can be selected by configuring the MODSEL 5 0 in PKCAU_CTL register The operation modes to be selected is shown in Table 2...

Page 973: ...tion operation is selected by configuring MODSEL 5 0 in PKCAU_CTL registeras 001001 Theoperationdeclarationis shownin Figure29 5 Arithmeticaddition The operation result is result A B Figure 29 5 Arithmetic addition Operand length L Operand A PKCAU RAM 0x404 Operand B offset address 0x408 0x400 0x8B4 0xA44 0xBD0 input output A B offset address 0xBD0 0 A 2 L 0 B 2 L 0 result 2 L 1 0 L 3136 Arithmeti...

Page 974: ... in PKCAU_CTL register as 001011 The operation declaration is shown in Figure 29 7 Arithmetic multiplication The operation result is result A B Figure 29 7 Arithmetic multiplication Operand length L Operand A PKCAU RAM 0x404 Operand B Offset address 0x408 0x400 0x8B4 0xA44 0xBD0 input output AxB Offset address 0xBD0 0 A 2 L 0 B 2 L 0 result 2 2L 0 L 3136 Arithmetic comparison The arithmetic compar...

Page 975: ...Offset address 0xBD0 0 A 2 L 0 B 2 L result 0x0 0x01 0x2 0 L 3136 Modular reduction The modular reduction operation is selected by configuring MODSEL 5 0 in PKCAU_CTL register as 001101 The operation declaration is shown in Figure 29 9 Modular reduction The operation result is result A mod n Figure 29 9 Modular reduction Modulus length M Operand A PKCAU RAM 0x404 Modulus n 0x408 Operand length L 0...

Page 976: ...ulus length M Operand A PKCAU RAM 0x404 Operand B 0x408 0x400 0x8B4 0xA44 0xD5C Modulus n 0xBD0 A B mod n Offset address input output Offset address 0xBD0 0 A n 0 B n 0 result n 0 n 2 M 0 M 3136 Modular subtraction The modular subtraction operation is selected by configuring MODSEL 5 0 in PKCAU_CTL register as 001111 The operation declaration is shown in Figure 29 11 Modular subtraction If A B the...

Page 977: ... use the Montgomery parameter R2 mod n to convert the operands to Montgomery residue system representation The Montgomery parameter calculation operation is selected by configuring MODSEL 5 0 in PKCAU_CTL register as 000001 The operation declaration is shown in Figure 29 12 Montgomery parameter calculation Figure 29 12 Montgomery parameter calculation Modulus length M PKCAU RAM 0x404 0x400 0xD5C M...

Page 978: ...A 2 Perform a modular multiplication operation A x B mod n 1 Calculate Montgomery parameter mont_para R2 mod n 2 Calculate AR A x mont_para mod n the output is in Montgomery domain 3 Calculate AB AR x B mod n the output is in natural domain Multiple modular multiplication A x B x C mod n 1 Calculate Montgomery parameter mont_para R2 mod n 2 Calculate AR A x mont_para mod n the output is in Montgom...

Page 979: ...g MODSEL 5 0 in PKCAU_CTL register as 000000 The operation declaration is shown in Figure 29 15 Modularexponentiation of normal mode The operation result is result A e mod n Figure 29 15 Modular exponentiation of normal mode Modulus length M Operand A PKCAU RAM 0x404 Exponent e 0x408 Exponent length L 0x400 0xA44 0xBD0 0xD5C Modulus n Ae mod n 0x724 Operand A 0xA44 Offset address input output Offs...

Page 980: ...0 A n 0 e n 0 result n 0 n 2 M 0 M 3136 0 Montgomery parameter R2 mod n n Modular inversion The Modular exponentiation of fast mode operation is selected by configuring MODSEL 5 0 in PKCAU_CTL register as 001000 The operation declaration is shown in Figure 29 17 Modular inversion The operation result is result A 1 mod n Figure 29 17 Modular inversion Modulus length M Operand A PKCAU RAM 0x404 Modu...

Page 981: ... exponentiation m A d mod pq more efficiently as follows m A d mod pq m1 A dP mod p m2 A dQ mod p h qinv m1 m2 mod p m1 m2 m m2 hq The operation declaration is shown in Figure 29 18 RSA CRT exponentiation The operation result is result A d mod pq Figure 29 18 RSA CRT exponentiation Operand length L Operand dP PKCAU RAM 0x404 Operand dQ 0x408 0x400 0x65C 0xBD0 0x7EC Prime p Prime q 0xD5C Operand qi...

Page 982: ...domain MODSEL 5 0 Operation modes 100000 Montgomery parameter computation then ECC scalar multiplication 100010 ECC scalar multiplication only Montgomery parameter must be loaded first 100100 ECDSA sign 100110 ECDSA verification 101000 Point on elliptic curve Fp check Point on elliptic curve Fp check The operationis usedtocheck whetherP x y is onthe y2 x3 ax b mod p inprimedomain whereA and B are ...

Page 983: ...nt on elliptic curve Fp check Parameters Range Input Modulus length M 0 M 640 Sign of curve coefficient a 0x0 positive 0x1 negative Curve coefficient a Absolute value a p Curve coefficient b Absolute value b p Curve modulus p Odd prime 0 p 2M x coordinate of point P x p y coordinate of point P y p ECC scalar multiplication ECC scalar multiplication operation is ak P xP yP where P is a point on the...

Page 984: ...EL 5 0 in PKCAU_CTL register as 100010 The operation declaration is shown in Figure 29 21 ECC scalar multiplication of fast mode Figure 29 21 ECC scalar multiplication of fast mode Modulus length M Curve coefficient a PKCAU RAM 0x404 Curve modulus p 0x408 Length of scalar multiplier k 0x400 Sign of curve coefficient a 0x40C 0x460 0x55C y coordinate of point P x coordinate of point P 0x5B0 scalar m...

Page 985: ...nt P yP p output x coordinate of point kP x p y coordinate of point kP y p If k 0 the output is a point at infinity When k is a multiple of curve prime order n the output will also be a point at infinity In this module output is 0 0 if the result is a point at infinity If k 0 the absolute value of k replaces k as the scalar multiplier for ECC scalar multiplication After the computation is complete...

Page 986: ...ERROR 0xEE8 Curve point kG coordinate x1 0x103C 0x1090 Curve point kG coordinate y1 extra outputs The range of parameters used ECDSA sign operation is shown in Table 29 7 Range of parametersused by ECDSA sign Table 29 7 Range of parametersused by ECDSA sign Parameters Range input Curve prime order n length LEN 0 LEN 640 Curve modulus p length M 0 M 640 Sign of curve coefficient a 0x0 positive 0x1 ...

Page 987: ...gister as 100110 The operation declaration is shown in Figure 29 23 ECDSA verification Figure 29 23 ECDSA verification Curve modulus p length M Curve coefficient a PKCAU RAM 0x4B4 Curve modulus p 0x45C Curve prime order n length 0x404 Sign of curve coefficient a 0x460 0x4B8 0x5E8 y coordinate of base point G x coordinate of base point G 0x63C Hash of message z 0xFE8 Curve prime order n Verificatio...

Page 988: ...order n prime n 2LEN output verification result 0x0 verification valid Not 0x0 verification invalid 29 3 6 PKCAU operation process The PKCAU can be enabled by setting the PKCAUEN bit in PKCAU_CTL register When the PKCAU is performing a calculation the PKCAUEN should not be cleared or else the ongoing operation is terminated and the content in PKCAU RAM will not be guaranteed WhenPKCAUENis 0 theapp...

Page 989: ... Montgomery parameter calculation mode by configuring the MODSEL 5 0 as 000001 then set START bit in PKCAU_CTL register 3 Wait for the ENDF bit set in PKCAU_STAT register 4 Read the Montgomery parameter from the PKCAU RAM then clear the ENDF bit by setting the ENDFC bit in PKCAU_STATC register 5 Load the initial data and Montgomery parameter into PKCAU RAM 6 Specify the operation to be performed i...

Page 990: ... 320 384 512 1024 2048 3072 3873 4658 7109 10330 14526 22301 79116 284359 626909 29 3 8 Status errors and interrupts There are several status and error flags in PKCAU and interrupt may be asserted from these flags by setting some register bits Access address error ADDRERR When the accessed address exceeds the expected range of PKCAU PKCAU RAM the address error flag ADDRERR bit in PKCAU_STAT regist...

Page 991: ...nbeclearedby settingtheENDFCbit inPKCAU_STATCregister The ENDF bit can also be cleared automatically if another operation is carried out by set the START bit The PKCAU interrupt events and flags are listed in Table 29 14 PKCAU interrupt requests Table 29 14 PKCAU interrupt requests Interrupt event Event flag Flag clear Enable control bit Access address error ADDRERR ADDRERRC ADDRERRIE RAM error RA...

Page 992: ...kept at reset value 20 ADDRERRIE Address error interrupt enable 0 Address error interrupt enable 1 Address error interrupt disable 19 RAMERRIE RAM error interrupt enable 0 RAM error interrupt enable 1 RAM error interrupt disable 18 Reserved Must be kept at reset value 17 ENDIE End of operation interrupt enable 0 End of operation interrupt enable 1 End of operation interrupt disable 16 14 Reserved ...

Page 993: ... Other values are reserved 7 2 Reserved Must be kept at reset value 1 START PKCAU starts operation This bit is set by softw are to start the PKCAU operation w hich is specified in MODSEL 5 0 in PKCAU_CTL register When the BUSY bit in PKCAU_STAT register is 1 w riting 1 to this bit w illbe ignored 0 PKCAUEN PKCAU enable 0 PKCAU disable 1 PKCAU enable 29 4 2 Status register PKCAU_STAT Address offset...

Page 994: ...ion is completed this bit is cleared by hardw are 15 0 Reserved Must be kept at reset value 29 4 3 Status clear register PKCAU_STATC Address offset 0x08 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved ADDRER RC RAMERR C Reserved ENDFC Reserved w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits Fields Descriptions ...

Page 995: ...GD32W51x User Manual 995 Softw are can clear the ENDF bit in PKCAU_STAT by w riting 1 to this bit 16 0 Reserved Must be kept at reset value ...

Page 996: ...ersampling rate decimation rate of Sinc filter can be configured sampling rate of configurable integrator Threshold monitor function independent Sinc filter configurableorder and oversampling rate decimation rate configurable data input source serial channel input data or HPDF output data Malfunction monitor function A counter with 8 bits is used to monitor the continuous 0 or 1 in the serial chan...

Page 997: ...unction monitor 0 1 s 0 s counter threshold Malfunction monitor 1 Interrupt break Interrupt break Configuration registers DMA Interrupt Break control Clock control Control unit Interrupts and events 1 end of conversion 2 threshold monitor 3 malfunction monitor 4 overflow Interrupt break Data output Data output The HPDF interfacecommunicateswiththeexternal Σ Δ modulatorby thepins in Table30 1 HPDF ...

Page 998: ...erial interface System clock The system clockfHPDFCLK of HPDF is usedtodrive channel transceiver digital filter integrator threshold monitor malfunction monitor extremum detector and control module The HPDF system clock source can be configured by the HPDFSEL bit in the ADDCTL register of the RCU chapter Serial input clock The serial interface of HPDF can receive clock signal from external sigma d...

Page 999: ...utput clock is 0 20MHz 30 3 4 Multiplex serial data channel HPDF has two multiplexing serial data channels which support SPI code and Manchester code The interface type supportedcan be selected for the current channel by configuring the SITYP 1 0 bit field in the HPDF_CHxCTL register SPI interface Under the standard SPI interface sigma delta modulator sends 1 bit data stream to theserial channel b...

Page 1000: ...KOUT signal into 2 frequencies to generate the serial input communication clock The data is sampled at the rising edge of every second CKOUT According to Table 30 2 SPI interface clock configuration the sequence diagram of SPI data transmission is shown in the figure below Figure 30 2 The sequence diagram of SPI data transmission SITYP 1 0 0 SPICKSS 1 0 0 SITYP 1 0 1 DATAINx CKINx Serial input clo...

Page 1001: ... data correctly configure the CKOUTDIV 7 0 frequency divider according to the expected flow rate of Manchester data The value of CKOUTDIV 7 0 is calculated with reference to the following format CKOUTDIV 1 XtHPDFCLK TManchester_clock 2xCKOUTDIV THPDFCLK 30 1 Serial communication coding synchronization After the serial channel is enabled the data can only be received correctly after successful sync...

Page 1002: ... a clock loss event occurs the clock loss flag bit CKLF will be set to 1 and a clock loss interrupt will be generated The corresponding interrupt flag bit can be cleared by setting CKLFC 1 0 bit field When the transceiver of the serial interface has not been synchronized the clock loss flag bit is set to 1 and cannot be cleared by the corresponding CKLFC 1 0 Therefore the correct steps to use the ...

Page 1003: ... SPI clock loss timing Note the maximum rate of Manchester encoded data stream must be less than the clock output CKOUT signal Channel pin redirection Channel pin redirection means that the pins of serial channel 0 can be configured as the pins of channel 1 that is channel 0 can read information from the DATAIN1 and CKIN1 pins Pin redirection is used to sampling audio data of PDM microphone The au...

Page 1004: ...the pulse skipper function can be used Pulse skipper refers to that the serial input data stream enters the filter after skipping a specified number of clock pulses so as to discard a certain number of bit bits This operation will cause the final output sample and the next sample from the filter to be calculated from the subsequent input data compared to the datastream that was not skipped The num...

Page 1005: ...sourceofthechannel TheCMSD 1 0 bit field in HPDF_CHxCTL is configured to determine whether the channel data input source is from serial data or parallel data Each channel provides a 32 bit parallel data input register HPDF_CHxPDI which canwrite two 16 bit parallel data by CPU DMA The register has two 16 bit data in signed format CPU DMAwrite parallel data There are two ways to write parallel data ...

Page 1006: ...nnel x 1 sampling In HPDF module only even channel channel0 supports dual channel mode If odd channel channel1 is configured as dual channel mode the parallel data input register HPDF_CHxPDI of this channel is write protected If channel x is even and configured as dual channel mode odd channel x 1 must be configured as standard mode The operation mode of HPDF_CHxPDI register is as follows Table 30...

Page 1007: ...ode and fast mode Continuousmode Set theRCCM bit to1 in HPDF_FLTyCTL0registertoenable continuous mode Incontinuous mode after the software starts the regular group conversion the conversion regular group channel conversion is repeated When the RCCM bit is cleared the regular conversion in continuous mode stops immediately Fast mode Enable fast mode by setting FAST bit to 1 in HPDF_FLTyCTL0 In fast...

Page 1008: ...ion also starts the inserted conversion 3 Trigger startup When the ICTSSEL 4 0 bit field in the HPDF_FLTyCTL0 register is written with a value other than 0 it indicates that trigger start is enabled and trigger signal source is selected at the same time The effective edge of the trigger is determined by the ICTEEN 1 0 bit field The trigger signals of the inserted group are shown in the following t...

Page 1009: ...ompleted the priority indicates the next step to perform regular conversion and the delayed start is indicated by the RCHPDT bit 30 3 8 Digital filter The digital filterof theHPDF moduleis ofSincX type Theinput datastream is filteredby SincX thereby reducingtheoutput datarateand increasingtheoutput dataresolution Configurethe order and oversampling rate decimation filtering of the SincX filter by ...

Page 1010: ...nitor the serial input data of the channel or the final output data after the channel conversion When the data reaches the thresholdset by thethresholdmonitor maximum orminimumthreshold aninterrupt orbreak event will be generated The maximum threshold is determined by the HTVAL 23 0 bits in HPDF_FLTyTMHT register and the minimum threshold is determined by the LTVAL 23 0 bits in HPDF_FLTyTMLT regis...

Page 1011: ...ta of the channel that is only the upper 16 bits of HTVAL 23 0 and LTVAL 23 0 define the threshold because theresolution of the threshold monitor filter is 16 bits In non fast mode of threshold monitor the final data of right shift and offset calibration will be compared with HTVAL 23 0 and LTVAL 23 0 Threshold monitor fast mode In fast mode the filter of the threshold monitor will be used and the...

Page 1012: ... equal to TMSFO 4 0 1 IOR 7 0 1 Threshold monitor flag The global state of the threshold monitor is the TMEOF flag in HPDF_FLTySTAT register When TMEOF 1 it indicates that at least one threshold monitor event has occurred that is an event that exceeds the upper lower limit threshold is generated If the threshold monitor event interrupt TMIE 1inHPDF_FLTyCTL1registeris enabled anthresholdmonitorinte...

Page 1013: ...y setting the MMEN bit in HPDF_CHxCTLregister Whenamalfunctionevent occurs onthechannel thecorresponding malfunctionmonitorflagMMF 1 0 is set Thecorrespondingflagcanbeclearedby MMFC 1 0 in HPDF_FLTyINTC If channel x is disabled CHEN 0 the hardware will also clear the malfunction monitor flag 30 3 12 Extremes monitor The extremes monitor is used to sample the minimum and maximum values peak to peak...

Page 1014: ...e fDATA is the parallel data rate of the CPU DMA input When the filter is bypassed fDATA fHPDFCLK must be satisfied Signed data format Signed data in HPDF module parallel data register regular and inserted group data register threshold monitor vlaue extreme monitor value and offset calibration are all signed formats The most significant bit of the output data indicates the sign of the value and th...

Page 1015: ...nitorinterrupt events malfunctionmonitorinterruptevents andchannel clocklossinterrupt events The specific interrupt event descriptionisasTable30 9 HPDF interruptevent shown Table 30 9 HPDF interrupt event Interrupt event description Clear Enable interrupt ICEF end of inserted conversion Read HPDF_FLTyIDATA register ICEIE RCEF end of regular conversion Read HPDF_FLTyRDATA register RCEIE ICDOF inser...

Page 1016: ...GD32W51x User Manual 1016 Figure 30 8 HPDF interrupt logic diagram ICEIE ICEF RCEIE RCEF ICDOIE ICDOF HTF LTF TMIE TMEOF MMIE MMF RCDOIE RCDOF CKLIE CKLF HPDF Interrupt ...

Page 1017: ...elds Descriptions 31 HPDFEN Global enable for HPDF interface 0 HPDF disabled 1 HPDF enabled If HPDFEN 0 the HPDF_FLTySTAT register and HPDF_FLTyTMSTAT register is set to reset state This bit is only available in HPDF_CH0CTL 30 CKOUTSEL Serial clock output source selection 0 Serial clock output source is from CK_HPDF clock 1 Serial clock output source is from CK_HPDFAUDIO clock This bit can be conf...

Page 1018: ...rce for channel x is taken from serial inputs 01 Reserved 10 Input data source for channel x is taken from internal HPDF_CHxPDI register 11 Reserved The HPDF_CHxPDI register is w rite protected w hen these bits are reset These bits can be configured only w hen CHEN 0 11 9 Reserved Must be kept at reset value 8 CHPINSEL Channel inputs pins selection 0 Channel inputs select pins of the current chann...

Page 1019: ...ing edge logic 1 falling edge logic 0 These bits can only be configured w hen CHEN 0 Channel x configuration register 0 HPDF_CHxCFG0 Address offset 0x04 0x20 x x 0 1 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CALOFF 23 8 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CALOFF 7 0 DTRS 4 0 Reserved rw rw Bits Fields Descriptions 3...

Page 1020: ...ilter oversampling rate decimation rate 0 31 The filter decimation rate equal to TMFOR 4 0 1 If TMFOR 0 the filter is bypassed These bits can be configured only w hen CHEN 0 in HPDF_CHxCTL register 15 14 Reserved Must be kept at reset value 13 12 MMBSD 1 0 Malfunction monitor break signal distribution 00 Break signal not is distributed to malfunction monitor on channel 01 Break signal 0 is distrib...

Page 1021: ...x20 x x 0 1 Reset value 0x0000 0000 This register has to be accessed by half word 16 bit and word 32 bit This register contains 16 bit input data to be processed by HPDF filter module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATAIN1 15 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATAIN0 15 0 rw Bits Fields Descriptions 31 16 DATAIN1 15 0 Data input for channel x or channel x 1 Data can be w ...

Page 1022: ... refer to 错误 未找到引用源 DATAIN0 15 0 is a signed format data Channel x pulse skip register HPDF_CHxPS Address offset 0x14 0x20 x x 0 1 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PLSK 5 0 rw Bits Fields Descriptions 31 6 Reserved Must be kept at reset value 5 0 PLSK 5 0 P...

Page 1023: ...version in continuous mode except for the first conversion is performed faster than the conversion in standard mode This bit has no effect on conversions w hich are not continuous This bit can be configured only w hen FLTEN 0 28 25 Reserved Must be kept at reset value 24 RCS Regular conversion channel selection 0 Channel 0 is selected as the regular conversion channel 1 Channel 1 is selected as th...

Page 1024: ...est to start an inserted conversion 10 Each falling edge on the trigger signal makes a request to start an inserted conversion 11 The edge rising edges and falling edges on the trigger signal make requests to start inserted conversions This bit can be configured only w hen FLTEN 0 12 8 ICTSSEL 4 0 Inserted conversions trigger signal selection 0x0 0x1F The value indicates that different trigger sig...

Page 1025: ...DF_FLT0 1 Launch an inserted conversion synchronously in HPDF_FLTyCTL0 w hen an inserted conversion is launched by SICC trigger in HPDF_FLT0CTL0 This bit can be configured only w hen FLTEN 0 2 Reserved Must be kept at reset value 1 SICC Start inserted group channel conversion 0 No effect 1 Makes a request to convert the channels in the inserted conversion group If ICPF 1 already invalid w rite to ...

Page 1026: ...ot monitor data from channel 0 and channel 1 01 Extremes monitor y monitor data from channel 0 10 Extremes monitor y monitor data from channel 1 11 Extremes monitor y monitor data from channel 0 and channel 1 7 Reserved Must be kept at reset value 6 CKLIE Clock loss interrupt enable 0 Detection of channel input clock loss interrupt is disabled 1 Detection of channel input clock loss interrupt is e...

Page 1027: ...3 2 1 0 Reserved RCPF ICPF Reserved TMEOF RCOF ICOF RCEF ICEF r r r r r r r Bits Fields Descriptions 31 26 Reserved Must be kept at reset value 25 24 MMF 1 0 Malfunction monitor flag 00 No malfunction event occurred on channel 0 and channel 1 01 Malfunction event occurred on channel 0 10 Malfunction event occurred on channel 1 11 Malfunction event occurred on channel 0 and channel 1 This bit is se...

Page 1028: ...est to start an inserted conversion is ignored When w rite 1 to SICC bit the ICPF w illbe setted 1 immediately 12 5 Reserved Must be kept at reset value 4 TMEOF Threshold monitor event occurred flag 0 No Threshold monitor event occurred 1 Threshold monitor event occurred w hich detected data crosses the threshold This bit is set by hardw are It is cleared by clearing HTF 1 0 and LTF 1 0 in HPDF_FL...

Page 1029: ...egister has to be accessed by word 32 bit Note The bits of HPDF_FLTyINTC are always read as 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved MMFC 1 0 Reserved CKLFC 1 0 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RCOFC ICOFC Reserved rc_w1 rc_w1 Bits Fields Descriptions 31 26 Reserved Must be kept at reset value 25 24 MMFC 1 0 Clear the malfunction monitor flag 00 No effec...

Page 1030: ...be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 15 4 3 2 1 0 Reserved ICGSEL 1 0 rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 0 ICGSEL 1 0 Inserted channel group selection 01 Channel 0 belongs to the inserted group 10 Channel 1 belongs to the inserted group 11 Channel 0 and channel 1 belong to the inserted gro...

Page 1031: ...register 28 26 Reserved Must be kept at reset value 25 16 SFOR 9 0 Sinc filter oversampling ratio decimation rate 0 1023 Sinc filter oversampling ratio decimation rate SFOR SFOR 9 0 1 If SFOR 9 0 0 SFOR 1 the filter w ill be bypass This bit can only be configured w hen FLTEN 0 in HPDF_FLTyCTL0 register 15 8 Reserved Must be kept at reset value 7 0 IOR 7 0 Integrator oversampling ratio 0 255 Integr...

Page 1032: ...ach a channel in the inserted group is converted ICCH is updated to indicate w hich channel w as converted Therefore IDATA 23 0 holds the data that corresponds to the channel indicated by ICCH Filter y regular channel conversion data register HPDF_FLTyRDATA Address offset 0x11C 0x80 y y 0 1 Reset value 0x0000 0000 This register has to be accessed by half word 16 bit or word 32 bit Note Half word a...

Page 1033: ...rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HTVAL 7 0 Reserved HTBSD 1 0 rw rw Bits Fields Descriptions 31 8 HTVAL 23 0 Threshold monitor high threshold value These bits are w ritten by softw are to determine the high threshold for the threshold monitor If TMFM 1 the higher 16 bits determine the 16 bit threshold as compared w ith the threshold monitor filter output Bits HTVAL 7 0 are ignored 7 2 Rese...

Page 1034: ...o low threshold event 01 Break signal 0 is distributed to low threshold event 10 Break signal 1 is distributed to low threshold event 11 Break signal 0 and 1 is distributed to low threshold event Filter y threshold monitor status register HPDF_FLTyTMSTAT Address offset 0x128 0x80 y y 0 1 Reset value 0x0000 0000 This register has to be accessed by word 32 bit Note All the bits of HPDF_FLTyTMSTAT ar...

Page 1035: ... 1 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved HTFC 1 0 Reserved LTFC 1 0 rc_w1 rc_w1 Bits Fields Descriptions 31 10 Reserved Must be kept at reset value 9 8 HTFC 1 0 Clear the threshold monitor high threshold flag 00 No effect 01 Clear the threshold monitor high thre...

Page 1036: ... this register 7 1 Reserved Must be kept at reset value 0 MAXDC Extremes monitor maximum data channel This bits indicate the channel on w hich the data is stored into MAXVAL 23 0 It can be cleared by reading of this register Filter y extremes monitor minimum register HPDF_FLTyEMMIN Address offset 0x134 0x80 y y 0 1 Reset value 0x7FFF FF00 This register has to be accessed by word 32 bit 31 30 29 28...

Page 1037: ...nual 1037 7 1 Reserved Must be kept at reset value 0 MINDC Extremes monitor minimum data channel This bit indicate the channel on w hich the data is stored into MINVAL 23 0 It can be cleared by reading of this register ...

Page 1038: ...ce modulation envelope signal and TIMER16 should generate high frequence carrier signal 31 3 Function overview IFRP is a module which is able to integrate the output of TIMER15 and TIMER16 to generate an infrared ray signal 1 The TIMER15 s CH0 is programed to generate the low frequence PWM signal which is the modulation envelope signal The TIMER16 s CH0 is programed to generate the high frquence P...

Page 1039: ...e Carrier TIMER15_CH0 s duty cycle can be changed and IFRP_OUT has inverted relationship with TIMER16_CH0 when TIMER15_CH0 is high Figure 31 3 IFRP output timechart 3 TIMER16_CH0 IFRP_OUT TIMER15_CH0 Note IFRP_OUT will keep the integrity of TIMER16_CH0 even if evelope signal TIMER15_CH0 is no active ...

Page 1040: ...high throughput HT Support for immediateACK and Block ACK policies Support for power management schemes including WMM power save power save multi poll PSMP and multiphase PSMP operation Interframe space timing support including RIFS Support for RTS CTS and CTS to self frame sequences for protecting frame exchanges Back off counters in hardware for supporting multiple priorities as specified in the...

Page 1041: ...150Mbps IEEE 802 11n mixed mode operation Per packet TXpower control Advanced channel estimation equalization automatic gain control CCA carrier symbol recovery and frame detection Digital calibrationalgorithms tohandleCMOSRF chipprocess voltage andtemperature PVT variations Per packet channel quality and signal strength measurements Compliance with FCC and other worldwide regulatory requirements ...

Page 1042: ...g 0 has no effect 33 2 List of terms Table 33 2 List of terms Glossary Descriptions Word Data of 32 bit length Half w ord Data of 16 bit length Byte Data of 8 bit length IAP in application programming Writing 0 has no effect IAP is the ability to re program the Flash memory of a microcontroller w hile the user program is running ICP in circuit programming ICP is the ability to program the Flash me...

Page 1043: ...GD32W51x User Manual 1043 34 Revision history Table 34 1 Revision history Revision No Description Date 1 0 Initial Release Nov 25 2021 ...

Page 1044: ...si ness industrial personal and or householdapplicationsonly TheProductsare not designed intended or auth orizedfor use ascomponents in systems designed or intended for the operation of weapons weapons systems nuclear installations atomic energy control instruments combustioncontrol instruments airplane or spaceship instruments transportation instrume nts traffic signal instruments life support de...

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