GD32W51x User Manual
621
Set by hardw are if the baud rate out of range or character comparison failed
Cleared by softw are, by w riting 1 to the ABDCMD bit in the USART_CMD register.
This bit is reserved in USART1.
13
Reserved
Must be kept at reset value
12
EBF
End of block flag
0: End of Block not reached
1: End of Block (number of characters) reached. An interrupt is generated if the
EBIE=1 in the USART_CTL1 register
Set by hardw are w hen the number of received bytes (from the start of the block,
including the prologue) is equal or greater than BLEN + 4.
Cleared by w riting 1 to EBC bit in USART_INTC register.
This bit is reserved in USART1.
11
RTF
Receiver timeout flag
0: Timeout value not reached
1: Timeout value reached w ithout any data reception. An interrupt is generated if
RTIE bit in the USART_CTL1 register is set.
Set by hardw are w hen the RT value, programmed in the USART_RT register has
lapsed w ithout any communication.
Cleared by w riting 1 to RTC bit in USART_INTC register.
The timeout corresponds to the CWT or BWT timings in smartcard mode.
This bit is reserved in USART1
10
CTS
CTS level
This bit equals to the inverted level of the nCTS input pin.
0: nCTS input pin is in high level
1: nCTS input pin is in low level
9
CTSF
CTS change flag
0: No change occurred on the nCTS status line
1: A change occurred on the nCTS status line. An interrupt w ill occur if the CTSIE
bit is set in USART_CTL2
Set by hardw are w hen the nCTS input toggles.
Cleared by w riting 1 to CTSC bit in USART_INTC register.
8
LBDF
LIN break detected flag
0: LIN Break is not detected
1: LIN Break is detected. An interrupt w ill occur if the LBDIE bit is set in
USART_CTL1
Set by hardw are w hen the LIN break is detected.
Cleared by w riting 1 to LBDC bit in USART_INTC register.
This bit is reserved in USART1.
7
TBE
Transmit data register empty
0: Data is not transferred to the shift register