GD32W51x User Manual
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4.3.5.
Cacheable and uncacheable access
ICACHE support memory region remapping feature, so as to make external memory
regions cacheable. ICACHE is able to access up to four external memory regions in
cacheable way. There is an alias of external memory region address in the code region
(address range [0x0000 0000:0x07FF FFFF] or [0x1000 0000:0x1FFF FFFF] ), so
ICACHE can manage and C-AHB bus is able to route external memory region (physical
address range [0x9000 0000:0x97FF FFFF]) through their code alias address.
Depending on memory request AHB transaction memory lookup attribute, which is shown
in
Table 4-3. ICACHE cache ability for transaction
, the request to ICACHE is defined as
cacheable or uncacheable.
Table 4-3. ICACHE cache ability for transaction
Lookup attribute
Cache ability
1
Cacheable
0
Uncacheable
If there is a memory request for external memory in the code region currently, ICACHE
operate the address remapping firstly. If the address is necessary to be aliased, remap
address firstly, and then cached. The target physical address does not need further
operation. The remapping functionality is remain available even if cache is disabled and
traffic is uncacheable.
If there is a memory uncacheable access, ICACHE is ignored, so that the AHB
transaction is transmitted directly unchanged to the master output port, while, depending
on remapping feature, only transaction address may be changed. The ignored operation
has no effect on accessing the target memory.
User is able to configure Cacheable memory regions in the memory protection unit (MPU),
which is responsible for the AHB attribute signal generating, the attribute is serve for any
transaction addressing a given region.
Table 4-4. memory configuration
m em ory
Cacheable
(
MPU Program m ing
)
Rem ap
(ICACHE_CFGx
Program m ing
)
Flash
Yes or No
Not required
SRAM
Not recommended
Not required
External memory
(
QSPI interface
)
Yes or No
Required
If ICACHE receive a cacheable transaction request, there are two scenes come out:
cache hit and cache miss.
Cache hit: If address is present in its TAG memory and the corresponding cache line is
valid, means cache hit, reading from cache and providing to core are in the same period.