GD32W51x User Manual
732
22.11.
Register definition
QSPI secure access base address: 0x5002 5800
QSPI non-secure access base address: 0x4002 5800
22.11.1.
Control register (QSPI_CTL)
Address offset: 0x00
Reset value: 0x0000 0010
This register can be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PSC[7:0]
SPMOD
SPS
Reserved
FL[4:0]
rw
rw
rw
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FMCMOD
BUSY
Reserved
FTL[3:0]
Reserved SCKDEN
SSAMPLE[1:0]
TMOUTE
N
Reserved ABORT
QSPIEN
r
r
rw
rw
rw
rw
w1s
rw
Bits
Fields
Descriptions
31:24
PSC [7:0]
This field defines the scaler factor for generating SCK based on the AHB clock
(value+1).
0: F
CLK
= F
AHB
,
1: F
CLK
= F
AHB
/2
2: F
CLK
= F
AHB
/3
...
255: F
CLK
= F
AHB
/256
For odd clock division factors, CLK’s duty cycle is not 50%. The clock signal remains
low one cycle longer than it stays high.
This field can be modified only w hen BUSY = 0.
23
SPMOD
Status Polling match mode
0: AND match mode. SM is set if all the unmasked bits received from the Flash
memory match the corresponding bits in the match register.
1: OR match mode. SM is set if any one of the unmasked bits received from the
Flash memory matches its corresponding bit in the match register.
This bit can be modified only w hen BUSY = 0.
22
SPS
Status polling mode stop
This bit determines if automatic polling is stopped after a match.
0: Status polling mode is stopped only by abort or by disabling the QSPI.
1: Status polling mode stops as soon as there is a match.
This bit can be modified only w hen BUSY = 0.