GD32W51x User Manual
411
Table 16-1. RTC register secure access rules
Access
m ode
Read
Write
Secure access
Nonsecure access
Secure access
Nonsecure access
RTCSECP =
0
Allow ed(except for
the backup
registers)
Allow ed access
RTC_SPM_CTL,
RTC_PPM_CTL,
RTC_NSMI_STA T,
RTC_TIME,
RTC_DATE,
RTC_SS, RTC_PSC,
RTC_COSC register
Allow ed(except for
the backup
registers)
Not allow ed
RTCSECP =
1
By configuring the INITSEC P, CALSECP, TSDSECP, WUTSECP, ALRM1SECP,
TAMPSECP, ALRM0SECP bit in RTC_SPM_CTL register, refer to
secure mode configuration summary
for details.
The summary of the RTC secured protected bits in RCU_SPM_CTL register is show as
the
Table 16-2. RTC secure mode configuration summary
.
Table 16-2. RTC secure mode configuration summary
Configuration bit in
RTC_SPM_CTL
Write in secure m ode
Read in secure m ode
Read in non-secure
m ode
INITSECP=0
Allow ed access
RTC_TIME, RTC_DATE
and TC_PSC register;
INITM in RTC_ICSR;
CR in RTC_CTL;
INITSECP in
RTC_SPM_CTL.
Allow ed access
RTC_TIME, RTC_DATE
and TC_PSC register;
INITM in RTC_ICSR;
CR control bits in
RTC_CTL;
INITSECP in
RTC_SPM_CTL.
Allow ed access
RTC_TIME,
RTC_DATE and
TC_PSC register;
INITM in RTC_ICSR;
CR control bits in
RTC_CTL;
INITSECP in
RTC_SPM_CTL.
CALSECP=0
Allow ed access
RTC_SHIFTCTL,
RTC_HRFC and
RTC_COSC registers;
A1H, S1H and REFEN
control bits in RTC_CTL;
CALCSECP in the
RTC_SPM_CTL.
Allow ed access
RTC_SHIFTCTL,
RTC_HRFC and
RTC_COSC registers;
A1H, S1H and REFEN
control bits in RTC_CTL;
CALCSECP in the
RTC_SPM_CTL.
Allow ed access
RTC_SHIFTCTL,
RTC_HRFC and
RTC_COSC registers;
A1H, S1H and REFEN
control bits in
RTC_CTL;
CALCSECP in the
RTC_SPM_CTL.
ALRM0SECP=0
Allow ed access
RTC_ALRM0TD,
RTC_ALRM0SS registers;
ALRM0EN, ALRM0IE in
RTC_CTL;
Allow ed access
RTC_ALRM0TD,
RTC_ALRM0SS
registers;
ALRM0EN, ALRM0IE in