Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
403
Figure 10-34. Result Value List Schema in Single Buffer Mode
While ADC is enabled, one Result Value List is active (indicated by bit RVL_SEL). The conversion Result
Value List can be read anytime. When the ADC is enabled the conversion result address registers
(ADCRBP, ADCCROFF_0/1, ADCRIDX) are read only and register ADCRIDX is under control of the
ADC.
A conversion result is always stored as 16bit entity in unsigned data representation. Left and right
justification inside the entity is selected via the DJM control bit. Unused bits inside an entity are stored
zero.
Table 10-32. Conversion Result Justification Overview
Conversion Resolution
(SRES[1:0])
Left Justified Result
(DJM = 1’b0)
Right Justified Result
(DJM = 1’b1)
8 bit
{Result[7:0],8’b00000000}
{8’b00000000,Result[7:0]}
10 bit
{Result[9:0],6’b000000}
{6’b000000,Result[9:0]}
12 bit
{Result[11:0],4’b0000}
{4’b0000,Result[11:0]}
Memory Map
0x00_0000
Register Space
RAM Space
RAM start address
RAM end address
RVL_0
(active)
(ADCCROFF_0)
(ADC
RVL_SEL = 1’b0 (forced by bit RVL_BMOD)
ADCRIDX(max))
Note:
Address register names in () are not absolute addresses instead they are a sample offset or sample index
