Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
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Freescale Semiconductor
Using Begin-Alignment together with opcode address comparisons, if the instruction is about to be
executed then the trace is started. If the trigger is at the address of a COF instruction, whilst tracing COF
addresses, then that COF address is stored to the trace buffer. If breakpoints are enabled, the breakpoint is
generated upon entry into State0 on completion of the tracing session; thus the breakpoint does not occur
at the instruction boundary.
6.4.5.1.2
Storing with Mid-Alignment
Storing with Mid-Alignment, data is stored in the trace buffer as soon as the DBG module is armed. When
the trigger condition is met, another 32 lines are traced before ending the tracing session, irrespective of
the number of lines stored before the trigger occurred, then the DBG module is disarmed and no more data
is stored. Using Mid-Alignment with opcode address triggers, if the instruction is about to be executed then
the trace is continued for another 32 lines. If breakpoints are enabled, the breakpoint is generated upon
entry into State0 on completion of the tracing session; thus the breakpoint does not occur at the instruction
boundary. When configured for Compressed Pure-PC tracing, the MAT info bit is set to indicate the last
PC entry before a trigger event.
6.4.5.1.3
Storing with End-Alignment
Storing with End-Alignment, data is stored in the trace buffer until the Final State is entered. Following
this trigger, the DBG module immediately transitions to State0. If the trigger is at the address of a COF
instruction the trigger event is not stored in the trace buffer.
6.4.5.2
Trace Modes
The DBG module can operate in four trace modes. The mode is selected using the TRCMOD bits in the
DBGTCRH register. Normal, Loop1 and Detail modes can be configured to store a timestamp with each
entry, by setting the STAMP bit. The modes are described in the following subsections.
In addition to the listed trace modes it is also possible to use code profiling to fill the trace buffer with a
highly compressed COF format. This can be subsequently read out in the same fashion as the listed trace
modes (see
).
6.4.5.2.1
Normal Mode
In Normal Mode, change of flow (COF) program counter (PC) addresses are stored.
CPU COF addresses are defined as follows:
•
Source address of taken conditional branches (bit-conditional, and loop primitives)
•
Destination address of indexed JMP and JSR instruction.s
•
Destination address of RTI and RTS instructions.
•
Vector address of interrupts
BRA, BSR, BGND as well as non-indexed JMP and JSR instructions are not classified as change of flow
and are not stored in the trace buffer.
COF addresses stored include the full address bus of CPU and an information byte, which contains bits to
indicate whether the stored address was a source, destination or vector address.
