Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 23 LIN Physical Layer (S12LINPHYV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 757
23.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the LIN Physical Layer.
23.3.1 Module Memory Map
A summary of the registers associated with the LIN Physical Layer module is shown in Table 23-2 .
Detailed descriptions of the registers and bits are given in the subsections that follow.
NOTE
Register Address = Module Base A Address Offset, where the
Module Base Address is defined at the MCU level and the Address Offset
is defined at the module level.
Address Offset
Register Name
Bit 7 6 5 4 3 2 1 Bit 0
0x0000
LPDR
R 0 0 0 0 0 0
LPDR1
LPDR0
W
0x0001
LPCR
R 0 0 0 0
LPE RXONLY LPWUE LPPUE
W
0x0002
Reserved
R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
0x0003
LPSLRM
R
LPDTDIS
0 0 0 0 0
LPSLR1 LPSLR0
W
0x0004
Reserved
R
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
W
0x0005
LPSR
R LPDT 0 0 0 0 0 0 0
W
0x0006
LPIE
R
LPDTIE LPOCIE
0 0 0 0 0 0
W
0x0007
LPIF
R
LPDTIF LPOCIF
0 0 0 0 0 0
W
Figure 23-2. Register Summary