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A full list of family members and options is included in the appendices.This document contains information
for all constituent modules, with the exception of the S12Z CPU. For S12ZCPU information please refer
to the CPU S12Z Reference Manual.
The following revision history table summarizes changes contained in this document. .
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Revision History
Date
Revision
Description
Sep, 2013
1.00
First release for external web site
- Add ZVHY 32K
- Update OSC etc. electrical spec
Nov, 2013
1.01
- Updated Appendix A electrical spec
- Updated SCI/ADC/SPI/BDC/FTMRZ sections (see section rev. history)
Mar, 2014
1.02
- Added ZVHL part and corresponding LINPHY information.
- Updated STOP mode BDC dependency text.
- Changed V
LVRXA
minimum from 2.97V to 2.95V
- Added frequency spec. for WSTAT to operating conditions table
- Removed incorrect device overview reference to over-temperature protection
- Corrected vector mapping of ADC CONIF_OIE interrupt
- Updated CPMU section (see section rev. history)
Jun, 2014
1.03
- Corrected ordering information controller family encoding in Appendix N
Sep, 2014
1.04
- Updated BKGD pin I/O specification
- Specified ADC accuracy for a range of VDDA and VREF
Jun, 2015
1.05
- Added reference to safety constrained applications
- Corrected ADC reference result to right justified
- Split VDDX electrical parameter into separate cases, with and without PNP
- Enhanced CPMU chapter (see CPMU revision history)
- Added startup from reset cycle count parameter
- Updated BATS electrical parameter values for LB1, HB1 and HB2.
- Corrected BKGD pin voltage condition in Table A-8
- Removed incorrect CPU feature from feature list
- Corrected BDC clock name (see BDC revision history)
