Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
182
Freescale Semiconductor
6.2
External Signal Description
6.2.1
External Event Input
The DBG module features an external event input signal, DBGEEV. The mapping of this signal to a device
pin is specified in the device specific documentation. This function can be enabled and configured by the
EEVE field in the DBGC1 control register. This signal is input only and allows an external event to force
a state sequencer transition, or trace buffer entry, or to gate trace buffer entries. With the external event
function enabled, a falling edge at the external event pin constitutes an event. Rising edges have no effect.
If configured for gating trace buffer entries, then a low level at the pin allows entries, but a high level
suppresses entries. The maximum frequency of events is half the internal core bus frequency. The function
is explained in the EEVE field description.
NOTE
Due to input pin synchronization circuitry, the DBG module sees external
events 2 bus cycles after they occur at the pin. Thus an external event
occurring less than 2 bus cycles before arming the DBG module is perceived
to occur whilst the DBG is armed.
When the device is in stop mode the synchronizer clocks are disabled and
the external events are ignored.
6.2.2
Profiling Output
The DBG module features a profiling data output signal PDO. The mapping of this signal to a device pin
is specified in the device specific documentation. The device pin is enabled for profiling by setting the
PDOE bit. The profiling function can be enabled by the PROFILE bit in the DBGTCRL control register.
This signal is output only and provides a serial, encoded data stream that can be used by external
development tools to reconstruct the internal CPU code flow, as specified in
profiling the device PDOCLK output is used as a clock signal.
6.3
Memory Map and Registers
6.3.1
Module Memory Map
A summary of the registers associated with the DBG module is shown in
. Detailed descriptions
of the registers and bits are given in the subsections that follow.
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0100
DBGC1
R
ARM
0
reserved
BDMBP
BRKCPU
reserved
EEVE
W
TRIG
0x0101
DBGC2
R
0
0
0
0
CDCM
ABCM
W
Figure 6-2. Quick Reference to DBG Registers
