Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
413
10.8.3
List Usage — CSL double buffer mode and RVL double buffer mode
In this use case both list types are configured for double buffer mode (CSL_BMOD=1’b1 and
RVL_BMOD=1’b1) and whenever a Command Sequence List (CSL) is finished or aborted the command
Sequence List is swapped by the simultaneous assertion of bits LDOK and RSTA.
Figure 10-37. CSL Double Buffer Mode — RVL Double Buffer Mode Diagram
This use case can be used if the channel order or CSL length varies very frequently in an application.
10.8.4
List Usage — CSL double buffer mode and RVL single buffer mode
In this use case the CSL is configured for double buffer mode (CSL_BMOD=1’b1) and the RVL is
configured for single buffer mode (RVL_BMOD=1’b0).
The two command lists can be different sizes and the allocated result list memory area in the RAM must
be able to hold as many entries as the larger of the two command lists. Each time when the end of a
Command Sequence List is reached, if bits LDOK and RSTA are set, the commands list is swapped.
Figure 10-38. CSL Double Buffer Mode — RVL Single Buffer Mode Diagram
CSL_0
CSL_1
RVL_0
RVL_1
CSL_0
CSL_1
RVL_0
RVL_1
(unused)
