Appendix P Detailed Register Address Map
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
864
Freescale Semiconductor
0x0714
SCI1SR1
R
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
W
0x0715
SCI1SR2
R
AMAP
0
0
TXPOL
RXPOL
BRK13
TXDIR
RAF
W
0x0716
SCI1DRH
R
R8
T8
0
0
0
0
0
0
W
0x0717
SCI1DRL
R
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
1 These registers are accessible if the AMAP bit in the SCI1SR2 register is set to zero.
2 These registers are accessible if the AMAP bit in the SCI1SR2 register is set to one.
0x0718–0x077F Reserved
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0718-
0x077F
Reserved
R
0
0
0
0
0
0
0
0
W
0x0780–0x0787 Serial Peripheral Interface (SPI0)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0780
SPI0CR1
R
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
W
0x0781
SPI0CR2
R
0
XFRW
0
MODFEN
BIDIROE
0
SPISWAI
SPC0
W
0x0782
SPI0BR
R
0
SPPR2
SPPR1
SPPR0
0
SPR2
SPR1
SPR0
W
0x0783
SPI0SR
R
SPIF
0
SPTEF
MODF
0
0
0
0
W
0x0784
SPI0DRH
R
R15
R14
R13
R12
R11
R10
R9
R8
T15
T14
T13
T12
T11
T10
T9
T8
0x0785
SPI0DRL
R
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
0x0786-
0x0787
Reserved
R
W
0x0710–0x0717 Serial Communication Interface (SCI1)