Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
330
Freescale Semiconductor
Read: Anytime
Write: Anytime
NOTE
PPOLx register bits can be written anytime. If the polarity is changed while
a PWM signal is being generated, a truncated or stretched pulse can occur
during the transition
9.3.2.3
PWM Clock Select Register (PWMCLK)
Each PWM channel has a choice of four clocks to use as the clock source for that channel as described
below.
Read: Anytime
Write: Anytime
NOTE
Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is
changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
Module Base + 0x0001
7
6
5
4
3
2
1
0
R
PPOL7
PPOL6
PPOL5
PPOL4
PPOL3
PPOL2
PPOL1
PPOL0
W
Reset
0
0
0
0
0
0
0
0
Figure 9-4. PWM Polarity Register (PWMPOL)
Table 9-3. PWMPOL Field Descriptions
Note:
Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero
Field
Description
7–0
PPOL[7:0]
P
ulse Width Channel 7–0 Polarity Bits
0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is reached.
1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is reached.
Module Base + 0x0002
7
6
5
4
3
2
1
0
R
PCLK7
PCLKL6
PCLK5
PCLK4
PCLK3
PCLK2
PCLK1
PCLK0
W
Reset
0
0
0
0
0
0
0
0
Figure 9-5. PWM Clock Select Register (PWMCLK)
