Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
191
Read: Anytime.
Write: Never.
6.3.2.7
Debug State Control Register 1 (DBGSCR1)
Read: Anytime.
Write: If DBG is not armed and PTACT is clear.
The state control register 1 selects the targeted next state whilst in State1. The matches refer to the outputs
of the comparator match control logic as depicted in
.
Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control
register.
Table 6-14. DBGCNT Field Descriptions
Field
Description
6–0
CNT[6:0]
Count Value
— The CNT bits [6:0] indicate the number of valid data lines stored in the trace buffer.
shows the correlation between the CNT bits and the number of valid data lines in the trace buffer. When the CNT
rolls over to zero, the TBF bit in DBGSR is set. Thereafter incrementing of CNT continues if configured for end-
alignment or mid-alignment.
The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT register is cleared by
power-on-reset initialization but is not cleared by other system resets. If a reset occurs during a debug session,
the DBGCNT register still indicates after the reset, the number of valid trace buffer entries stored before the reset
occurred. The DBGCNT register is not decremented when reading from the trace buffer.
Table 6-15. CNT Decoding Table
TBF (DBGSR)
CNT[6:0]
Description
0
0000000
No data valid
0
0000001
32 bits of one line valid
0
0000010
0000100
0000110
..
1111100
1 line valid
2 lines valid
3 lines valid
..
62 lines valid
0
1111110
63 lines valid
1
0000000
64 lines valid; if using Begin trigger alignment,
ARM bit is cleared and the tracing session ends.
1
0000010
..
1111110
64 lines valid,
oldest data has been overwritten by most recent data
Address: 0x0107
7
6
5
4
3
2
1
0
R
C3SC1
C3SC0
C2SC1
C2SC0
C1SC1
C1SC0
C0SC1
C0SC0
W
Reset
0
0
0
0
0
0
0
0
Figure 6-9. Debug State Control Register 1 (DBGSCR1)
