Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 331
The clock source of each PWM channel is determined by PCLKx bits in PWMCLK and PCLKABx bits
in PWMCLKAB (see
Section 9.3.2.7, “PWM Clock A/B Select Register (PWMCLKAB) ). For Channel
0, 1, 4, 5, the selection is shown in Table 9-5 ; For Channel 2, 3, 6, 7, the selection is shown in Table 9-6 .
Table 9-5. PWM Channel 0, 1, 4, 5 Clock Source Selection
Table 9-6. PWM Channel 2, 3, 6, 7 Clock Source Selection
9.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)
This register selects the prescale clock source for clocks A and B independently.
Read: Anytime
Write: Anytime
NOTE
PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock
pre-scale is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
Table 9-4. PWMCLK Field Descriptions
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero
Field Description
7-0
PCLK[7:0]
Pulse Width Channel 7-0 Clock Select
0 Clock A or B is the clock source for PWM channel 7-0, as shown in Table 9-5 and Table 9-6 .
1 Clock SA or SB is the clock source for PWM channel 7-0, as shown in Table 9-5 and Table 9-6 .
PCLKAB[0,1,4,5] PCLK[0,1,4,5] Clock Source Selection
0 0 Clock A
0 1 Clock SA
1 0 Clock B
1 1 Clock SB
PCLKAB[2,3,6,7] PCLK[2,3,6,7] Clock Source Selection
0 0 Clock B
0 1 Clock SB
1 0 Clock A
1 1 Clock SA
Module Base + 0x0003
7 6 5 4 3 2 1 0
R 0
PCKB2 PCKB1 PCKB0
0
PCKA2 PCKA1 PCKA0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 9-6. PWM Prescale Clock Select Register (PWMPRCLK)