Chapter 18 Real-Time Counter With Calendar (RTCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
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Freescale Semiconductor
The second counter rolls over to 0 after reaching 23.
18.5
Functional Description
The RTC module support calendar functions. It includes a main 16-bit up-counter with a
16-bit modulo
register. The module also contains software selectable interrupt logic and clock output for compensation
calibration.
The RTC module provides clock indications in seconds, minutes, hours. Reading the calendar registers
return the current time. Writing to these registers set the time, and the counters will continue to count from
the new settings.
18.5.1
RTC clock and reset behavior
Depending on the use case, the RTC clock can derived from OSCCLK or OSCCLK_32K. After power on
reset, the RTC clock is derived from OSCCLK. User should set the RTCPS and CLKSRC value before
enabling the RTCEN. If RTCCLK is from OSCCLK, the RTCPS value should be set to meet that the
prescaler clock frequency will be 1MHz. The 1MHz clock will follow by a 1/32 divider to generate a
31.25KHz clock, which will be used as RTC counter clock(RTCCNT clock input). In case the clock source
is OSCCLK, after reset, the main OSC will be disabled and must be enabled by setting the OSCE in CPMU
as soon as possible in order to have clock available for the RTC. If clock source is OSCCLK_32K,
software must wait the OSC startup time after power on reset before enabling the RTC. If 32K OSC is
enabled, it will be always on until a power on reset happens.
18.5.2 Calendar Functions
Calendar functions are provided by the second, minute and hour count registers. The second, minute and
hour counters are able to generate interrupts on every count increment, providing periodic interrupts for
the second (RTCSECF), minute (RTCMINF) and hour (RTCHRF). A CPU interrupt request is generated
if the corresponding enable bit (SECIE, MINIE and HRIE) is also set.
18.5.3 Interrupts
In addition to the second, minute and hour periodic interrupts generated by the clock functions, the
7
6
5
4
3
2
1
0
R
0
0
0
HR4
HR3
HR2
HR1
HR0
W
POR:
0
0
0
0
0
0
0
0
Figure 18-12. Hour Register (HRR)
Table 18-13. HRR Field Descriptions
Field
Description
4:0
HR4~HR0
Hour Counter Value
— These read/write bits contains the current value of the hour. 0 to 23 is valid.Wirting the
value other than 0 to 23 has no effect.
