Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
Freescale Semiconductor
247
7.3.2.6
S12CPMU_UHV_V5 Interrupt Enable Register (CPMUINT)
This register enables S12CPMU_UHV_V5 interrupt requests.
Read: Anytime
Write: Anytime
Module Base + 0x0008
7
6
5
4
3
2
1
0
R
RTIE
0
0
LOCKIE
0
0
OSCIE
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-9. S12CPMU_UHV_V5 Interrupt Enable Register (CPMUINT)
Table 7-6. CPMUINT Field Descriptions
Field
Description
7
RTIE
Real Time Interrupt Enable Bit
0 Interrupt requests from RTI are disabled.
1 Interrupt will be requested whenever RTIF is set.
4
LOCKIE
PLL Lock Interrupt Enable Bit
0 PLL LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
1
OSCIE
Oscillator Corrupt Interrupt Enable Bit
0 Oscillator Corrupt interrupt requests are disabled.
1 Interrupt will be requested whenever OSCIF is set.
