Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
248
Freescale
Semiconductor
7.3.2.7
S12CPMU_UHV_V5 Clock Select Register (CPMUCLKS)
This register controls S12CPMU_UHV_V5 clock selection.
Read: Anytime
Write:
•
Only possible if PROT=0 (CPMUPROT register) in all MCU Modes (Normal and Special Mode).
•
All bits in Special Mode (if PROT=0).
•
PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: In Normal Mode (if PROT=0).
•
CSAD: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
•
COPOSCSEL0: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
If COPOSCSEL0 was cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL0=1 or
insufficient OSCCLK quality), then COPOSCSEL0 can be set once again.
•
COPOSCSEL1: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
COPOSCSEL1 will not be cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL1=1
or insufficient OSCCLK quality if OSCCLK is used as clock source for other clock domains: for
instance core clock etc.).
NOTE
After writing CPMUCLKS register, it is strongly recommended to read
back CPMUCLKS register to make sure that write of PLLSEL,
RTIOSCSEL and COPOSCSEL was successful. This is because under
certain circumstances writes have no effect or bits are automatically
changed (see CPMUCLKS register and bit descriptions).
NOTE
When using the oscillator clock as system clock (write PLLSEL = 0) it is
highly recommended to enable the oscillator clock monitor reset feature
(write OMRE = 1 in CPMUOSC2 register). If the oscillator monitor reset
feature is disabled (OMRE = 0) and the oscillator clock is used as system
clock, the system will stall in case of loss of oscillation.
Module Base + 0x0009
7
6
5
4
3
2
1
0
R
PLLSEL
PSTP
CSAD
COP
OSCSEL1
PRE
PCE
RTI
OSCSEL
COP
OSCSEL0
W
Reset
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-10. S12CPMU_UHV_V5 Clock Select Register (CPMUCLKS)
