Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 2 Port Integration Module (S12ZVHYPIMV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 109
2.4.2.1 Data register (PTx)
This register holds the value driven out to the pin if the pin is used as a general-purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general-purpose output. When
reading this address, the synchronized state of the pin is returned if the associated data direction register
bits are configured as input.
If the data direction register bits are configured as output, the contents of the data register is returned. This
is independent of any other configuration (
Figure 2-24 ).
2.4.2.2 Input register (PTIx)
This register is read-only and always returns the synchronized state of the pin ( Figure 2-24 ).
2.4.2.3 Data direction register (DDRx)
This register defines whether the pin is used as an general-purpose input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored ( Figure 2-24 ).
Independent of the pin usage with a peripheral module this register determines the source of data when
reading the associated data register address (
Section 2.4.2.1, “Data register (PTx)“ ”).
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on port data or port input registers, when
changing the data direction register.
1. To use the digital input function the related bit in Digital Input Enable Register (DIENADx) must be set to logic level
“1”. To use the digital input function the related bit in Slew Rate Register (SRRx) must be set to logic level “0”.