Chapter 4 Interrupt (S12ZINTV0)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
139
I-bit maskable interrupt requests cannot be interrupted by other I-bit maskable interrupt requests per
default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the
I-bit in the CCW (CLI). After clearing the I-bit, I-bit maskable interrupt requests with higher priority can
interrupt the current ISR.
An ISR of an interruptible I-bit maskable interrupt request could basically look like this:
•
Service interrupt, e.g., clear interrupt flags, copy data, etc.
•
Clear I-bit in the CCW by executing the CPU instruction CLI (thus allowing interrupt requests with
higher priority)
•
Process data
•
Return from interrupt by executing the instruction RTI
Figure 4-14. Interrupt Processing Example
4.5.3
Wake Up from Stop or Wait Mode
4.5.3.1
CPU Wake Up from Stop or Wait Mode
Every I-bit maskable interrupt request which is configured to be handled by the CPU is capable of waking
the MCU from stop or wait mode. Additionally machine exceptions can wake-up the MCU from stop or
wait mode.
To determine whether an I-bit maskable interrupts is qualified to wake up the CPU or not, the same settings
as in normal run mode are applied during stop or wait mode:
•
If the I-bit in the CCW is set, all I-bit maskable interrupts are masked from waking up the MCU.
•
An I-bit maskable interrupt is ignored if it is configured to a priority level below or equal to the
current IPL in CCW.
The X-bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if
the X-bit in CCW is set
1
. If the X-bit maskable interrupt request is used to wake-up the MCU with the X-
0
Reset
4
0
7
6
5
4
3
2
1
0
L4
7
0
4
L1 (Pending)
L7
L3 (Pending)
RTI
4
0
3
0
RTI
RTI
1
0
0
RTI
Stacked IPL
Processing Levels
IPL in CCW
