Chapter 23 LIN Physical Layer (S12LINPHYV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
758
Freescale Semiconductor
23.3.2
Register Descriptions
This section describes all the LIN Physical Layer registers and their individual bits.
23.3.2.1
Port LP Data Register (LPDR)
Table 23-2. LPDR Field Description
Module Base + Address 0x0000
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
LPDR1
LPDR0
W
Reset
0
0
0
0
0
0
1
1
= Unimplemented
Figure 23-3. Port LP Data Register (LPDR)
Field
Description
1
LPDR1
Port LP Data Bit 1
— The LIN Physical Layer LPTxD input (see
) can be directly controlled by this
register bit. The routing of the LPTxD input is done in the Port Inetrgation Module (PIM). Please refer to the PIM
chapter of the device Reference Manual for more info.
0
LPDR0
Port LP Data Bit 0
— Read-only bit. The LIN Physical Layer LPRxD output state can be read at any time.
