Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
194
Freescale Semiconductor
In the case of simultaneous matches, the match on the higher channel number (3....0) has priority.
6.3.2.10
Debug Event Flag Register (DBGEFR)
Read: Anytime.
Write: Never
DBGEFR contains flag bits each mapped to events whilst armed. Should an event occur, then the
corresponding flag is set. With the exception of TRIGF, the bits can only be set when the ARM bit is set.
The TRIGF bit is set if a TRIG event occurs when ARM is already set, or if the TRIG event occurs
simultaneous to setting the ARM bit.All other flags can only be cleared by arming the DBG module. Thus
the contents are retained after a debug session for evaluation purposes.
A set flag does not inhibit the setting of other flags.
7–6
C3SC[1:0]
Channel 3 State Control.
If EEVE !=10, these bits select the targeted next state whilst in State3 following a match3.
If EEVE =10, these bits select the targeted next state whilst in State3 following an external event.
Table 6-21. State3 Match State Sequencer Transitions
CxSC[1:0]
Function
00
Match has no effect
01
Match forces sequencer to State1
10
Match forces sequencer to State2
11
Match forces sequencer to Final State
Address: 0x010A
7
6
5
4
3
2
1
0
R
PTBOVF
TRIGF
0
EEVF
ME3
ME2
ME1
ME0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-12. Debug Event Flag Register (DBGEFR)
Table 6-22. DBGEFR Field Descriptions
Field
Description
7
PTBOVF
Profiling Trace Buffer Overflow Flag
— Indicates the occurrence of a trace buffer overflow event during a
profiling session.
0 No trace buffer overflow event
1 Trace buffer overflow event
6
TRIGF
TRIG Flag
— Indicates the occurrence of a TRIG event during the debug session.
0 No TRIG event
1 TRIG event
Table 6-20. DBGSCR3 Field Descriptions (continued)
Field
Description
