Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Appendix L SPI Electrical Specifications
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
820 Freescale Semiconductor
Figure L-4. SPI Slave Timing (CPHA=0)
In Figure L-5. the timing diagram for slave mode with transmission format CPHA=1 is depicted.
Figure L-5. SPI Slave Timing (CPHA=1)
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
SS
(INPUT)
1
9
5 6
MSB IN
BIT 6 . . . 1
LSB IN
SLAVE MSB
SLAVE LSB OUT
BIT 6 . . . 1
11
4 4
2
7
(CPOL

0)
(CPOL

1)
3
13
NOTE: Not defined!
12
12
11
see
13
note
8
10
see
note
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
1
5 6
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT SLAVE LSB OUT
BIT 6 . . . 1
4 4
9
12 13
11
(CPOL

0)
(CPOL

1)
SS
(INPUT)
2
12 13
3
NOTE: Not defined!
SLAVE
7
8
see
note