Chapter 1 Device Overview MC9S12ZVHY/MC9S12ZVHL Families
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
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1.7.2.14
PP[7:0] — Port P I/O Signals
PP[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. Out of reset the pull devices are disabled.
1.7.2.15
PS[7:0] / KWS[7:0] — Port S I/O signals
PS[7:0] are general-purpose input or output signals. The signals can be configured on per signal basis as
interrupt inputs with wake-up capability (KWS[7:0]). These signals can have a pull-up or pull-down
device selected and enabled on per signal basis. The signals can be configured on per signals basis as open
drain output. Out of reset the pull-up devices are enabled.
1.7.2.16
PT[7:0] / KWT[7:0] — Port T I/O signals
PT[7:0] are general-purpose input or output signals. The signals can be configured on per signal basis as
interrupt inputs with wake-up capability (KWT[7:0]). These signals can have a pull-up or pull-down
device selected and enabled on per signal basis. Out of reset the pull devices are disabled.
1.7.2.17
PU[7:0] — Port U I/O Signals
PU[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. They can have a slew rate enabled per signal basis also. Out of reset the
pull devices are disabled.
1.7.2.18
AN0_[7:0] — ADC0 Input Signals
AN0_[7:0] are the analog inputs of the Analog-to-Digital Converters.
1.7.2.19
VRH, VRL — ADC0 Reference Signals
VRH and VRL are the reference voltage input pins for the analog-to-digital converter.
1.7.2.20
SPI0 Signals
1.7.2.20.1
SS0 Signal
This signal is associated with the slave select SS functionality of the serial peripheral interface SPI0.
1.7.2.20.2
SCK0 Signal
This signal is associated with the serial clock SCK functionality of the serial peripheral interface SPI0.
1.7.2.20.3
MISO0 Signal
This signal is associated with the MISO functionality of the serial peripheral interface SPI0. This signal
acts as master input during master mode or as slave output during slave mode.
