Freescale Semiconductor MC9S12ZVHL32, Reference Manual

Page: 208 / 874

Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
208 Freescale Semiconductor
If the comparator INST bit is set, the comparator address register contents are compared with the PC, the
data register contents and access type bits are ignored. The comparator address register must be loaded
with the address of the first opcode byte.
6.4.2.2 Address and Data Comparator Match
Comparators A and C feature data comparators, for data access comparisons. The comparators do not
evaluate if accessed data is valid. Accesses across aligned 32-bit boundaries are split internally into
consecutive accesses. The data comparator mapping to accessed addresses for the CPU is shown in
Table 6-42 , whereby the Address column refers to the lowest 2 bits of the lowest accessed address. This
corresponds to the most significant data byte.
The fixed mapping of data comparator bytes to addresses within a 32-bit data field ensures data matches
independent of access size. To compare a single data byte within the 32-bit field, the other bytes within
that field must be masked using the corresponding data mask registers. This ensures that any access of that
byte (32-bit,16-bit or 8-bit) with matching data causes a match. If no bytes are masked then the data
comparator always compares all 32-bits and can only generate a match on a 32-bit access with correct 32-
bit data value. In this case, 8-bit or 16-bit accesses within the 32-bit field cannot generate a match even if
the contents of the addressed bytes match because all 32-bits must match. In
Table 6-43 the Access
Address column refers to the address bits[1:0] of the lowest accessed address (most significant data byte).
Table 6-43. Data Register Use Dependency On CPU Access Type
8-bit ADDR[n] Match No Match No Match No Match
Table 6-42. Comparator Data Byte Alignment
Address[1:0] Data Comparator
00 DBGxD0
01 DBGxD1
10 DBGxD2
11 DBGxD3
Memory Address[2:0]
Case
Access
Address
Access
Size
000 001 010 011 100 101 110
1 00 32-bit DBGxD0 DBGxD1 DBGxD2 DBGxD3
2 01 32-bit DBGxD1 DBGxD2 DBGxD3 DBGxD0
3 10 32-bit DBGxD2 DBGxD3 DBGxD0 DBGxD1
4 11 32-bit DBGxD3 DBGxD0 DBGxD1 DBGxD2
5 00 16-bit DBGxD0 DBGxD1
6 01 16-bit DBGxD1 DBGxD2
7 10 16-bit DBGxD2 DBGxD3
8 11 16-bit DBGxD3 DBGxD0
Table 6-41. Comparator Address Bus Matches
Access Address ADDR[n] ADDR[n+1] ADDR[n+2] ADDR[n+3]